Microchip Technology Inc.
ATSAMDA1E14B
2024.06.03
Microchip ATSAMDA1E14B Microcontroller
CM0+
r0p0
selectable
true
2
false
8
32
AC
Analog Comparators
AC
0x0
0x0
0x22
registers
n
0x0
0x22
registers
n
0x0
0x22
registers
n
0x0
0x22
registers
n
AC_INTREQ
24
AC
24
COMPCTRL0
Comparator Control n
0x10
32
read-write
n
0x0
0x0
ENABLE
Enable
0
1
FLEN
Filter Length
24
3
FLENSelect
OFF
No filtering
0
MAJ3
3-bit majority function (2 of 3)
1
MAJ5
5-bit majority function (3 of 5)
2
HYST
Hysteresis Enable
19
1
INTSEL
Interrupt Selection
5
2
INTSELSelect
TOGGLE
Interrupt on comparator output toggle
0
RISING
Interrupt on comparator output rising
1
FALLING
Interrupt on comparator output falling
2
EOC
Interrupt on end of comparison (single-shot mode only)
3
MUXNEG
Negative Input Mux Selection
8
3
MUXNEGSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
GND
Ground
4
VSCALE
VDD scaler
5
BANDGAP
Internal bandgap voltage
6
DAC
DAC output
7
MUXPOS
Positive Input Mux Selection
12
2
MUXPOSSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
OUT
Output
16
2
OUTSelect
OFF
The output of COMPn is not routed to the COMPn I/O port
0
ASYNC
The asynchronous output of COMPn is routed to the COMPn I/O port
1
SYNC
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
2
SINGLE
Single-Shot Mode
1
1
SPEED
Speed Selection
2
2
SPEEDSelect
LOW
Low speed
0
HIGH
High speed
1
SWAP
Swap Inputs and Invert
15
1
COMPCTRL1
Comparator Control n
0x14
32
read-write
n
0x0
0x0
ENABLE
Enable
0
1
FLEN
Filter Length
24
3
FLENSelect
OFF
No filtering
0
MAJ3
3-bit majority function (2 of 3)
1
MAJ5
5-bit majority function (3 of 5)
2
HYST
Hysteresis Enable
19
1
INTSEL
Interrupt Selection
5
2
INTSELSelect
TOGGLE
Interrupt on comparator output toggle
0
RISING
Interrupt on comparator output rising
1
FALLING
Interrupt on comparator output falling
2
EOC
Interrupt on end of comparison (single-shot mode only)
3
MUXNEG
Negative Input Mux Selection
8
3
MUXNEGSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
GND
Ground
4
VSCALE
VDD scaler
5
BANDGAP
Internal bandgap voltage
6
DAC
DAC output
7
MUXPOS
Positive Input Mux Selection
12
2
MUXPOSSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
OUT
Output
16
2
OUTSelect
OFF
The output of COMPn is not routed to the COMPn I/O port
0
ASYNC
The asynchronous output of COMPn is routed to the COMPn I/O port
1
SYNC
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
2
SINGLE
Single-Shot Mode
1
1
SPEED
Speed Selection
2
2
SPEEDSelect
LOW
Low speed
0
HIGH
High speed
1
SWAP
Swap Inputs and Invert
15
1
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
LPMUX
Low-Power Mux
7
1
RUNSTDBY
Run in Standby
2
1
SWRST
Software Reset
0
1
write-only
CTRLB
Control B
0x1
8
write-only
n
0x0
0x0
START0
Comparator 0 Start Comparison
0
1
START1
Comparator 1 Start Comparison
1
1
EVCTRL
Event Control
0x2
16
read-write
n
0x0
0x0
COMPEI0
Comparator 0 Event Input
8
1
COMPEI1
Comparator 1 Event Input
9
1
COMPEO0
Comparator 0 Event Output Enable
0
1
COMPEO1
Comparator 1 Event Output Enable
1
1
WINEO0
Window 0 Event Output Enable
4
1
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
COMP0
Comparator 0 Interrupt Enable
0
1
COMP1
Comparator 1 Interrupt Enable
1
1
WIN0
Window 0 Interrupt Enable
4
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
COMP0
Comparator 0 Interrupt Enable
0
1
COMP1
Comparator 1 Interrupt Enable
1
1
WIN0
Window 0 Interrupt Enable
4
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
COMP0
Comparator 0
0
1
COMP1
Comparator 1
1
1
WIN0
Window 0
4
1
SCALER0
Scaler n
0x20
8
read-write
n
0x0
0x0
VALUE
Scaler Value
0
6
SCALER1
Scaler n
0x21
8
read-write
n
0x0
0x0
VALUE
Scaler Value
0
6
STATUSA
Status A
0x8
8
read-only
n
0x0
0x0
STATE0
Comparator 0 Current State
0
1
STATE1
Comparator 1 Current State
1
1
WSTATE0
Window 0 Current State
4
2
WSTATE0Select
ABOVE
Signal is above window
0
INSIDE
Signal is inside window
1
BELOW
Signal is below window
2
STATUSB
Status B
0x9
8
read-only
n
0x0
0x0
READY0
Comparator 0 Ready
0
1
read-only
READY1
Comparator 1 Ready
1
1
read-only
SYNCBUSY
Synchronization Busy
7
1
STATUSC
Status C
0xA
8
read-only
n
0x0
0x0
STATE0
Comparator 0 Current State
0
1
STATE1
Comparator 1 Current State
1
1
WSTATE0
Window 0 Current State
4
2
WSTATE0Select
ABOVE
Signal is above window
0
INSIDE
Signal is inside window
1
BELOW
Signal is below window
2
WINCTRL
Window Control
0xC
8
read-write
n
0x0
0x0
WEN0
Window 0 Mode Enable
0
1
WINTSEL0
Window 0 Interrupt Selection
1
2
WINTSEL0Select
ABOVE
Interrupt on signal above window
0
INSIDE
Interrupt on signal inside window
1
BELOW
Interrupt on signal below window
2
OUTSIDE
Interrupt on signal outside window
3
ADC
Analog Digital Converter
ADC
0x0
0x0
0x2B
registers
n
0x0
0x2B
registers
n
0x0
0x2B
registers
n
0x0
0x2B
registers
n
ADC_INTREQ
23
ADC
23
AVGCTRL
Average Control
0x2
8
read-write
n
0x0
0x0
ADJRES
Adjusting Result / Division Coefficient
4
3
SAMPLENUM
Number of Samples to be Collected
0
4
SAMPLENUMSelect
1
1 sample
0x0
2
2 samples
0x1
4
4 samples
0x2
8
8 samples
0x3
16
16 samples
0x4
32
32 samples
0x5
64
64 samples
0x6
128
128 samples
0x7
256
256 samples
0x8
512
512 samples
0x9
1024
1024 samples
0xA
CALIB
Calibration
0x28
16
read-write
n
0x0
0x0
BIAS_CAL
Bias Calibration Value
8
3
LINEARITY_CAL
Linearity Calibration Value
0
8
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
RUNSTDBY
Run in Standby
2
1
SWRST
Software Reset
0
1
CTRLB
Control B
0x4
16
read-write
n
0x0
0x0
CORREN
Digital Correction Logic Enabled
3
1
DIFFMODE
Differential Mode
0
1
FREERUN
Free Running Mode
2
1
LEFTADJ
Left-Adjusted Result
1
1
PRESCALER
Prescaler Configuration
8
3
PRESCALERSelect
DIV4
Peripheral clock divided by 4
0x0
DIV8
Peripheral clock divided by 8
0x1
DIV16
Peripheral clock divided by 16
0x2
DIV32
Peripheral clock divided by 32
0x3
DIV64
Peripheral clock divided by 64
0x4
DIV128
Peripheral clock divided by 128
0x5
DIV256
Peripheral clock divided by 256
0x6
DIV512
Peripheral clock divided by 512
0x7
RESSEL
Conversion Result Resolution
4
2
RESSELSelect
12BIT
12-bit result
0x0
16BIT
16-bit averaging mode
0x1
10BIT
10-bit result
0x2
8BIT
8-bit result
0x3
DBGCTRL
Debug Control
0x2A
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
EVCTRL
Event Control
0x14
8
read-write
n
0x0
0x0
RESRDYEO
Result Ready Event Out
4
1
STARTEI
Start Conversion Event In
0
1
SYNCEI
Synchronization Event In
1
1
WINMONEO
Window Monitor Event Out
5
1
GAINCORR
Gain Correction
0x24
16
read-write
n
0x0
0x0
GAINCORR
Gain Correction Value
0
12
INPUTCTRL
Input Control
0x10
32
read-write
n
0x0
0x0
GAIN
Gain Factor Selection
24
4
GAINSelect
1X
1x
0x0
2X
2x
0x1
4X
4x
0x2
8X
8x
0x3
16X
16x
0x4
DIV2
1/2x
0xF
INPUTOFFSET
Positive Mux Setting Offset
20
4
INPUTSCAN
Number of Input Channels Included in Scan
16
4
MUXNEG
Negative Mux Input Selection
8
5
MUXNEGSelect
PIN0
ADC AIN0 Pin
0x0
PIN1
ADC AIN1 Pin
0x1
GND
Internal Ground
0x18
IOGND
I/O Ground
0x19
PIN2
ADC AIN2 Pin
0x2
PIN3
ADC AIN3 Pin
0x3
PIN4
ADC AIN4 Pin
0x4
PIN5
ADC AIN5 Pin
0x5
PIN6
ADC AIN6 Pin
0x6
PIN7
ADC AIN7 Pin
0x7
MUXPOS
Positive Mux Input Selection
0
5
MUXPOSSelect
PIN0
ADC AIN0 Pin
0x0
PIN1
ADC AIN1 Pin
0x1
PIN16
ADC AIN16 Pin
0x10
PIN17
ADC AIN17 Pin
0x11
PIN18
ADC AIN18 Pin
0x12
PIN19
ADC AIN19 Pin
0x13
TEMP
Temperature Reference
0x18
BANDGAP
Bandgap Voltage
0x19
SCALEDCOREVCC
1/4 Scaled Core Supply
0x1A
SCALEDIOVCC
1/4 Scaled I/O Supply
0x1B
DAC
DAC Output
0x1C
PIN2
ADC AIN2 Pin
0x2
PIN3
ADC AIN3 Pin
0x3
PIN4
ADC AIN4 Pin
0x4
PIN5
ADC AIN5 Pin
0x5
PIN6
ADC AIN6 Pin
0x6
PIN7
ADC AIN7 Pin
0x7
PIN8
ADC AIN8 Pin
0x8
PIN9
ADC AIN9 Pin
0x9
PIN10
ADC AIN10 Pin
0xA
PIN11
ADC AIN11 Pin
0xB
PIN12
ADC AIN12 Pin
0xC
PIN13
ADC AIN13 Pin
0xD
PIN14
ADC AIN14 Pin
0xE
PIN15
ADC AIN15 Pin
0xF
INTENCLR
Interrupt Enable Clear
0x16
8
read-write
n
0x0
0x0
OVERRUN
Overrun Interrupt Enable
1
1
RESRDY
Result Ready Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
WINMON
Window Monitor Interrupt Enable
2
1
INTENSET
Interrupt Enable Set
0x17
8
read-write
n
0x0
0x0
OVERRUN
Overrun Interrupt Enable
1
1
RESRDY
Result Ready Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
WINMON
Window Monitor Interrupt Enable
2
1
INTFLAG
Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
OVERRUN
Overrun
1
1
RESRDY
Result Ready
0
1
SYNCRDY
Synchronization Ready
3
1
WINMON
Window Monitor
2
1
OFFSETCORR
Offset Correction
0x26
16
read-write
n
0x0
0x0
OFFSETCORR
Offset Correction Value
0
12
REFCTRL
Reference Control
0x1
8
read-write
n
0x0
0x0
REFCOMP
Reference Buffer Offset Compensation Enable
7
1
REFSEL
Reference Selection
0
4
REFSELSelect
INT1V
1.0V voltage reference
0x0
INTVCC0
1/1.48 VDDANA
0x1
INTVCC1
1/2 VDDANA (only for VDDANA > 2.0V)
0x2
AREFA
External reference A
0x3
AREFB
External reference B
0x4
RESULT
Result
0x1A
16
read-only
n
0x0
0x0
RESULT
Result Conversion Value
0
16
read-only
SAMPCTRL
Sampling Time Control
0x3
8
read-write
n
0x0
0x0
SAMPLEN
Sampling Time Length
0
6
STATUS
Status
0x19
8
read-only
n
0x0
0x0
SYNCBUSY
Synchronization Busy
7
1
read-only
SWTRIG
Software Trigger
0xC
8
read-write
n
0x0
0x0
FLUSH
ADC Conversion Flush
0
1
START
ADC Start Conversion
1
1
WINCTRL
Window Monitor Control
0x8
8
read-write
n
0x0
0x0
WINMODE
Window Monitor Mode
0
3
WINMODESelect
DISABLE
No window mode (default)
0x0
MODE1
Mode 1: RESULT > WINLT
0x1
MODE2
Mode 2: RESULT < WINUT
0x2
MODE3
Mode 3: WINLT < RESULT < WINUT
0x3
MODE4
Mode 4: !(WINLT < RESULT < WINUT)
0x4
WINLT
Window Monitor Lower Threshold
0x1C
16
read-write
n
0x0
0x0
WINLT
Window Lower Threshold
0
16
WINUT
Window Monitor Upper Threshold
0x20
16
read-write
n
0x0
0x0
WINUT
Window Upper Threshold
0
16
DAC
Digital Analog Converter
DAC
0x0
0x0
0xE
registers
n
0x0
0xE
registers
n
0x0
0xE
registers
n
0x0
0xE
registers
n
DAC_INTREQ
25
DAC
25
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
RUNSTDBY
Run in Standby
2
1
SWRST
Software Reset
0
1
CTRLB
Control B
0x1
8
read-write
n
0x0
0x0
BDWP
Bypass DATABUF Write Protection
4
1
EOEN
External Output Enable
0
1
IOEN
Internal Output Enable
1
1
LEFTADJ
Left Adjusted Data
2
1
REFSEL
Reference Selection
6
2
REFSELSelect
INT1V
Internal 1.0V reference
0
AVCC
AVCC
1
VREFP
External reference
2
VPD
Voltage Pump Disable
3
1
DATA
Data
0x8
16
read-write
n
0x0
0x0
DATA
Data value to be converted
0
16
DATABUF
Data Buffer
0xC
16
read-write
n
0x0
0x0
DATABUF
Data Buffer
0
16
EVCTRL
Event Control
0x2
8
read-write
n
0x0
0x0
EMPTYEO
Data Buffer Empty Event Output
1
1
STARTEI
Start Conversion Event Input
0
1
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty Interrupt Enable
1
1
SYNCRDY
Synchronization Ready Interrupt Enable
2
1
UNDERRUN
Underrun Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty Interrupt Enable
1
1
SYNCRDY
Synchronization Ready Interrupt Enable
2
1
UNDERRUN
Underrun Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty
1
1
SYNCRDY
Synchronization Ready
2
1
UNDERRUN
Underrun
0
1
STATUS
Status
0x7
8
read-only
n
0x0
0x0
SYNCBUSY
Synchronization Busy Status
7
1
read-only
DMAC
Direct Memory Access Controller
DMAC
0x0
0x0
0x50
registers
n
0x0
0x50
registers
n
0x0
0x50
registers
n
0x0
0x50
registers
n
DMAC_INTREQ
6
DMAC
6
ACTIVE
Active Channel and Levels
0x30
32
read-only
n
0x0
0x0
ABUSY
Active Channel Busy
15
1
read-only
BTCNT
Active Channel Block Transfer Count
16
16
read-only
ID
Active Channel ID
8
5
read-only
LVLEX0
Level 0 Channel Trigger Request Executing
0
1
read-only
LVLEX1
Level 1 Channel Trigger Request Executing
1
1
read-only
LVLEX2
Level 2 Channel Trigger Request Executing
2
1
read-only
LVLEX3
Level 3 Channel Trigger Request Executing
3
1
read-only
BASEADDR
Descriptor Memory Section Base Address
0x34
32
read-write
n
0x0
0x0
BASEADDR
Descriptor Memory Base Address
0
32
BUSYCH
Busy Channels
0x28
32
read-only
n
0x0
0x0
BUSYCH0
Busy Channel 0
0
1
read-only
BUSYCH1
Busy Channel 1
1
1
read-only
BUSYCH10
Busy Channel 10
10
1
read-only
BUSYCH11
Busy Channel 11
11
1
read-only
BUSYCH2
Busy Channel 2
2
1
read-only
BUSYCH3
Busy Channel 3
3
1
read-only
BUSYCH4
Busy Channel 4
4
1
read-only
BUSYCH5
Busy Channel 5
5
1
read-only
BUSYCH6
Busy Channel 6
6
1
read-only
BUSYCH7
Busy Channel 7
7
1
read-only
BUSYCH8
Busy Channel 8
8
1
read-only
BUSYCH9
Busy Channel 9
9
1
read-only
CHCTRLA
Channel Control A
0x40
8
read-write
n
0x0
0x0
ENABLE
Channel Enable
1
1
SWRST
Channel Software Reset
0
1
CHCTRLB
Channel Control B
0x44
32
read-write
n
0x0
0x0
CMD
Software Command
24
2
CMDSelect
NOACT
No action
0x0
SUSPEND
Channel suspend operation
0x1
RESUME
Channel resume operation
0x2
EVACT
Event Input Action
0
3
EVACTSelect
NOACT
No action
0x0
TRIG
Transfer and periodic transfer trigger
0x1
CTRIG
Conditional transfer trigger
0x2
CBLOCK
Conditional block transfer
0x3
SUSPEND
Channel suspend operation
0x4
RESUME
Channel resume operation
0x5
SSKIP
Skip next block suspend action
0x6
EVIE
Channel Event Input Enable
3
1
EVOE
Channel Event Output Enable
4
1
LVL
Channel Arbitration Level
5
2
LVLSelect
LVL0
Channel Priority Level 0
0x00
LVL1
Channel Priority Level 1
0x01
LVL2
Channel Priority Level 2
0x02
LVL3
Channel Priority Level 3
0x03
TRIGACT
Trigger Action
22
2
TRIGACTSelect
BLOCK
One trigger required for each block transfer
0x0
BEAT
One trigger required for each beat transfer
0x2
TRANSACTION
One trigger required for each transaction
0x3
TRIGSRC
Peripheral Trigger Source
8
6
TRIGSRCSelect
DISABLE
Only software/event triggers
0x00
CHID
Channel ID
0x3F
8
read-write
n
0x0
0x0
ID
Channel ID
0
4
CHINTENCLR
Channel Interrupt Enable Clear
0x4C
8
read-write
n
0x0
0x0
SUSP
Channel Suspend Interrupt Enable
2
1
TCMPL
Transfer Complete Interrupt Enable
1
1
TERR
Transfer Error Interrupt Enable
0
1
CHINTENSET
Channel Interrupt Enable Set
0x4D
8
read-write
n
0x0
0x0
SUSP
Channel Suspend Interrupt Enable
2
1
TCMPL
Transfer Complete Interrupt Enable
1
1
TERR
Transfer Error Interrupt Enable
0
1
CHINTFLAG
Channel Interrupt Flag Status and Clear
0x4E
8
read-write
n
0x0
0x0
SUSP
Channel Suspend
2
1
TCMPL
Transfer Complete
1
1
TERR
Transfer Error
0
1
CHSTATUS
Channel Status
0x4F
8
read-only
n
0x0
0x0
BUSY
Channel Busy
1
1
read-only
FERR
Fetch Error
2
1
read-only
PEND
Channel Pending
0
1
read-only
CRCCHKSUM
CRC Checksum
0x8
32
read-write
n
0x0
0x0
CRCCHKSUM
CRC Checksum
0
32
CRCCTRL
CRC Control
0x2
16
read-write
n
0x0
0x0
CRCBEATSIZE
CRC Beat Size
0
2
CRCBEATSIZESelect
BYTE
Byte bus access
0x0
HWORD
Half-word bus access
0x1
WORD
Word bus access
0x2
CRCPOLY
CRC Polynomial Type
2
2
CRCPOLYSelect
CRC16
CRC-16 (CRC-CCITT)
0x0
CRC32
CRC32 (IEEE 802.3)
0x1
CRCSRC
CRC Input Source
8
6
CRCSRCSelect
NOACT
No action
0x00
IO
I/O interface
0x01
CRCDATAIN
CRC Data Input
0x4
32
read-write
n
0x0
0x0
CRCDATAIN
CRC Data Input
0
32
CRCSTATUS
CRC Status
0xC
8
read-write
n
0x0
0x0
CRCBUSY
CRC Module Busy
0
1
CRCZERO
CRC Zero
1
1
read-only
CTRL
Control
0x0
16
read-write
n
0x0
0x0
CRCENABLE
CRC Enable
2
1
DMAENABLE
DMA Enable
1
1
LVLEN0
Priority Level 0 Enable
8
1
LVLEN1
Priority Level 1 Enable
9
1
LVLEN2
Priority Level 2 Enable
10
1
LVLEN3
Priority Level 3 Enable
11
1
SWRST
Software Reset
0
1
DBGCTRL
Debug Control
0xD
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
INTPEND
Interrupt Pending
0x20
16
read-write
n
0x0
0x0
BUSY
Busy
14
1
read-only
FERR
Fetch Error
13
1
read-only
ID
Channel ID
0
4
PEND
Pending
15
1
read-only
SUSP
Channel Suspend
10
1
TCMPL
Transfer Complete
9
1
TERR
Transfer Error
8
1
INTSTATUS
Interrupt Status
0x24
32
read-only
n
0x0
0x0
CHINT0
Channel 0 Pending Interrupt
0
1
read-only
CHINT1
Channel 1 Pending Interrupt
1
1
read-only
CHINT10
Channel 10 Pending Interrupt
10
1
read-only
CHINT11
Channel 11 Pending Interrupt
11
1
read-only
CHINT2
Channel 2 Pending Interrupt
2
1
read-only
CHINT3
Channel 3 Pending Interrupt
3
1
read-only
CHINT4
Channel 4 Pending Interrupt
4
1
read-only
CHINT5
Channel 5 Pending Interrupt
5
1
read-only
CHINT6
Channel 6 Pending Interrupt
6
1
read-only
CHINT7
Channel 7 Pending Interrupt
7
1
read-only
CHINT8
Channel 8 Pending Interrupt
8
1
read-only
CHINT9
Channel 9 Pending Interrupt
9
1
read-only
PENDCH
Pending Channels
0x2C
32
read-only
n
0x0
0x0
PENDCH0
Pending Channel 0
0
1
read-only
PENDCH1
Pending Channel 1
1
1
read-only
PENDCH10
Pending Channel 10
10
1
read-only
PENDCH11
Pending Channel 11
11
1
read-only
PENDCH2
Pending Channel 2
2
1
read-only
PENDCH3
Pending Channel 3
3
1
read-only
PENDCH4
Pending Channel 4
4
1
read-only
PENDCH5
Pending Channel 5
5
1
read-only
PENDCH6
Pending Channel 6
6
1
read-only
PENDCH7
Pending Channel 7
7
1
read-only
PENDCH8
Pending Channel 8
8
1
read-only
PENDCH9
Pending Channel 9
9
1
read-only
PRICTRL0
Priority Control 0
0x14
32
read-write
n
0x0
0x0
LVLPRI0
Level 0 Channel Priority Number
0
4
LVLPRI1
Level 1 Channel Priority Number
8
4
LVLPRI2
Level 2 Channel Priority Number
16
4
LVLPRI3
Level 3 Channel Priority Number
24
4
RRLVLEN0
Level 0 Round-Robin Scheduling Enable
7
1
RRLVLEN1
Level 1 Round-Robin Scheduling Enable
15
1
RRLVLEN2
Level 2 Round-Robin Scheduling Enable
23
1
RRLVLEN3
Level 3 Round-Robin Scheduling Enable
31
1
QOSCTRL
QOS Control
0xE
8
read-write
n
0x0
0x0
DQOS
Data Transfer Quality of Service
4
2
DQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
FQOS
Fetch Quality of Service
2
2
FQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
WRBQOS
Write-Back Quality of Service
0
2
WRBQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
SWTRIGCTRL
Software Trigger Control
0x10
32
read-write
n
0x0
0x0
SWTRIG0
Channel 0 Software Trigger
0
1
SWTRIG1
Channel 1 Software Trigger
1
1
SWTRIG10
Channel 10 Software Trigger
10
1
SWTRIG11
Channel 11 Software Trigger
11
1
SWTRIG2
Channel 2 Software Trigger
2
1
SWTRIG3
Channel 3 Software Trigger
3
1
SWTRIG4
Channel 4 Software Trigger
4
1
SWTRIG5
Channel 5 Software Trigger
5
1
SWTRIG6
Channel 6 Software Trigger
6
1
SWTRIG7
Channel 7 Software Trigger
7
1
SWTRIG8
Channel 8 Software Trigger
8
1
SWTRIG9
Channel 9 Software Trigger
9
1
WRBADDR
Write-Back Memory Section Base Address
0x38
32
read-write
n
0x0
0x0
WRBADDR
Write-Back Memory Base Address
0
32
DSU
Device Service Unit
DSU
0x0
0x0
0x2000
registers
n
ADDR
Address
0x4
32
read-write
n
0x0
0x0
ADDR
Address
2
30
CID0
Component Identification 0
0x1FF0
32
read-only
n
0x0
0x0
PREAMBLEB0
Preamble Byte 0
0
8
read-only
CID1
Component Identification 1
0x1FF4
32
read-only
n
0x0
0x0
CCLASS
Component Class
4
4
read-only
PREAMBLE
Preamble
0
4
read-only
CID2
Component Identification 2
0x1FF8
32
read-only
n
0x0
0x0
PREAMBLEB2
Preamble Byte 2
0
8
read-only
CID3
Component Identification 3
0x1FFC
32
read-only
n
0x0
0x0
PREAMBLEB3
Preamble Byte 3
0
8
CTRL
Control
0x0
8
write-only
n
0x0
0x0
CE
Chip Erase
4
1
write-only
CRC
32-bit Cyclic Redundancy Check
2
1
write-only
MBIST
Memory Built-In Self-Test
3
1
write-only
SWRST
Software Reset
0
1
write-only
DATA
Data
0xC
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC0
Debug Communication Channel n
0x10
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC1
Debug Communication Channel n
0x14
32
read-write
n
0x0
0x0
DATA
Data
0
32
DID
Device Identification
0x18
32
read-only
n
0x0
0x0
DEVSEL
Device Select
0
8
read-only
DIE
Die Identification
12
4
read-only
FAMILY
Product Family
23
5
read-only
PROCESSOR
Processor
28
4
read-only
REVISION
Revision
8
4
read-only
SERIES
Product Series
16
6
read-only
END
CoreSight ROM Table End
0x1008
32
read-only
n
0x0
0x0
END
End Marker
0
32
ENTRY0
CoreSight ROM Table Entry 0
0x1000
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
read-only
EPRES
Entry Present
0
1
FMT
Format
1
1
read-only
ENTRY1
CoreSight ROM Table Entry 1
0x1004
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
read-only
EPRES
Entry Present
0
1
FMT
Format
1
1
read-only
LENGTH
Length
0x8
32
read-write
n
0x0
0x0
LENGTH
Length
2
30
MEMTYPE
CoreSight ROM Table Memory Type
0x1FCC
32
read-only
n
0x0
0x0
SMEMP
System Memory Present
0
1
PID0
Peripheral Identification 0
0x1FE0
32
read-only
n
0x0
0x0
PARTNBL
Part Number Low
0
8
PID1
Peripheral Identification 1
0x1FE4
32
read-only
n
0x0
0x0
JEPIDCL
Low part of the JEP-106 Identity Code
4
4
read-only
PARTNBH
Part Number High
0
4
PID2
Peripheral Identification 2
0x1FE8
32
read-only
n
0x0
0x0
JEPIDCH
JEP-106 Identity Code High
0
3
JEPU
JEP-106 Identity Code is used
3
1
read-only
REVISION
Revision Number
4
4
read-only
PID3
Peripheral Identification 3
0x1FEC
32
read-only
n
0x0
0x0
CUSMOD
ARM CUSMOD
0
4
REVAND
Revision Number
4
4
read-only
PID4
Peripheral Identification 4
0x1FD0
32
read-only
n
0x0
0x0
FKBC
4KB Count
4
4
read-only
JEPCC
JEP-106 Continuation Code
0
4
STATUSA
Status A
0x1
8
read-write
n
0x0
0x0
BERR
Bus Error
2
1
CRSTEXT
CPU Reset Phase Extension
1
1
DONE
Done
0
1
FAIL
Failure
3
1
PERR
Protection Error
4
1
STATUSB
Status B
0x2
8
read-only
n
0x0
0x0
DBGPRES
Debugger Present
1
1
DCCD0
Debug Communication Channel 0 Dirty
2
1
DCCD1
Debug Communication Channel 1 Dirty
3
1
HPE
Hot-Plugging Enable
4
1
PROT
Protected
0
1
EIC
External Interrupt Controller
EIC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
EIC_INTREQ
4
EIC
4
CONFIG0
Configuration n
0x18
32
read-write
n
0x0
0x0
FILTEN0
Filter 0 Enable
3
1
FILTEN1
Filter 1 Enable
7
1
FILTEN2
Filter 2 Enable
11
1
FILTEN3
Filter 3 Enable
15
1
FILTEN4
Filter 4 Enable
19
1
FILTEN5
Filter 5 Enable
23
1
FILTEN6
Filter 6 Enable
27
1
FILTEN7
Filter 7 Enable
31
1
SENSE0
Input Sense 0 Configuration
0
3
SENSE0Select
NONE
No detection
0
RISE
Rising-edge detection
1
FALL
Falling-edge detection
2
BOTH
Both-edges detection
3
HIGH
High-level detection
4
LOW
Low-level detection
5
SENSE1
Input Sense 1 Configuration
4
3
SENSE1Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE2
Input Sense 2 Configuration
8
3
SENSE2Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE3
Input Sense 3 Configuration
12
3
SENSE3Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE4
Input Sense 4 Configuration
16
3
SENSE4Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE5
Input Sense 5 Configuration
20
3
SENSE5Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE6
Input Sense 6 Configuration
24
3
SENSE6Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE7
Input Sense 7 Configuration
28
3
SENSE7Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
CONFIG1
Configuration n
0x1C
32
read-write
n
0x0
0x0
FILTEN0
Filter 0 Enable
3
1
FILTEN1
Filter 1 Enable
7
1
FILTEN2
Filter 2 Enable
11
1
FILTEN3
Filter 3 Enable
15
1
FILTEN4
Filter 4 Enable
19
1
FILTEN5
Filter 5 Enable
23
1
FILTEN6
Filter 6 Enable
27
1
FILTEN7
Filter 7 Enable
31
1
SENSE0
Input Sense 0 Configuration
0
3
SENSE0Select
NONE
No detection
0
RISE
Rising-edge detection
1
FALL
Falling-edge detection
2
BOTH
Both-edges detection
3
HIGH
High-level detection
4
LOW
Low-level detection
5
SENSE1
Input Sense 1 Configuration
4
3
SENSE1Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE2
Input Sense 2 Configuration
8
3
SENSE2Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE3
Input Sense 3 Configuration
12
3
SENSE3Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE4
Input Sense 4 Configuration
16
3
SENSE4Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE5
Input Sense 5 Configuration
20
3
SENSE5Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE6
Input Sense 6 Configuration
24
3
SENSE6Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE7
Input Sense 7 Configuration
28
3
SENSE7Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
CTRL
Control
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
EVCTRL
Event Control
0x4
32
read-write
n
0x0
0x0
EXTINTEO0
External Interrupt 0 Event Output Enable
0
1
EXTINTEO1
External Interrupt 1 Event Output Enable
1
1
EXTINTEO10
External Interrupt 10 Event Output Enable
10
1
EXTINTEO11
External Interrupt 11 Event Output Enable
11
1
EXTINTEO12
External Interrupt 12 Event Output Enable
12
1
EXTINTEO13
External Interrupt 13 Event Output Enable
13
1
EXTINTEO14
External Interrupt 14 Event Output Enable
14
1
EXTINTEO15
External Interrupt 15 Event Output Enable
15
1
EXTINTEO2
External Interrupt 2 Event Output Enable
2
1
EXTINTEO3
External Interrupt 3 Event Output Enable
3
1
EXTINTEO4
External Interrupt 4 Event Output Enable
4
1
EXTINTEO5
External Interrupt 5 Event Output Enable
5
1
EXTINTEO6
External Interrupt 6 Event Output Enable
6
1
EXTINTEO7
External Interrupt 7 Event Output Enable
7
1
EXTINTEO8
External Interrupt 8 Event Output Enable
8
1
EXTINTEO9
External Interrupt 9 Event Output Enable
9
1
INTENCLR
Interrupt Enable Clear
0x8
32
read-write
n
0x0
0x0
EXTINT0
External Interrupt 0 Enable
0
1
EXTINT1
External Interrupt 1 Enable
1
1
EXTINT10
External Interrupt 10 Enable
10
1
EXTINT11
External Interrupt 11 Enable
11
1
EXTINT12
External Interrupt 12 Enable
12
1
EXTINT13
External Interrupt 13 Enable
13
1
EXTINT14
External Interrupt 14 Enable
14
1
EXTINT15
External Interrupt 15 Enable
15
1
EXTINT2
External Interrupt 2 Enable
2
1
EXTINT3
External Interrupt 3 Enable
3
1
EXTINT4
External Interrupt 4 Enable
4
1
EXTINT5
External Interrupt 5 Enable
5
1
EXTINT6
External Interrupt 6 Enable
6
1
EXTINT7
External Interrupt 7 Enable
7
1
EXTINT8
External Interrupt 8 Enable
8
1
EXTINT9
External Interrupt 9 Enable
9
1
INTENSET
Interrupt Enable Set
0xC
32
read-write
n
0x0
0x0
EXTINT0
External Interrupt 0 Enable
0
1
EXTINT1
External Interrupt 1 Enable
1
1
EXTINT10
External Interrupt 10 Enable
10
1
EXTINT11
External Interrupt 11 Enable
11
1
EXTINT12
External Interrupt 12 Enable
12
1
EXTINT13
External Interrupt 13 Enable
13
1
EXTINT14
External Interrupt 14 Enable
14
1
EXTINT15
External Interrupt 15 Enable
15
1
EXTINT2
External Interrupt 2 Enable
2
1
EXTINT3
External Interrupt 3 Enable
3
1
EXTINT4
External Interrupt 4 Enable
4
1
EXTINT5
External Interrupt 5 Enable
5
1
EXTINT6
External Interrupt 6 Enable
6
1
EXTINT7
External Interrupt 7 Enable
7
1
EXTINT8
External Interrupt 8 Enable
8
1
EXTINT9
External Interrupt 9 Enable
9
1
INTFLAG
Interrupt Flag Status and Clear
0x10
32
read-write
n
0x0
0x0
EXTINT0
External Interrupt 0
0
1
EXTINT1
External Interrupt 1
1
1
EXTINT10
External Interrupt 10
10
1
EXTINT11
External Interrupt 11
11
1
EXTINT12
External Interrupt 12
12
1
EXTINT13
External Interrupt 13
13
1
EXTINT14
External Interrupt 14
14
1
EXTINT15
External Interrupt 15
15
1
EXTINT2
External Interrupt 2
2
1
EXTINT3
External Interrupt 3
3
1
EXTINT4
External Interrupt 4
4
1
EXTINT5
External Interrupt 5
5
1
EXTINT6
External Interrupt 6
6
1
EXTINT7
External Interrupt 7
7
1
EXTINT8
External Interrupt 8
8
1
EXTINT9
External Interrupt 9
9
1
NMICTRL
Non-Maskable Interrupt Control
0x2
8
read-write
n
0x0
0x0
NMIFILTEN
Non-Maskable Interrupt Filter Enable
3
1
NMISENSE
Non-Maskable Interrupt Sense
0
3
NMISENSESelect
NONE
No detection
0
RISE
Rising-edge detection
1
FALL
Falling-edge detection
2
BOTH
Both-edges detection
3
HIGH
High-level detection
4
LOW
Low-level detection
5
NMIFLAG
Non-Maskable Interrupt Flag Status and Clear
0x3
8
read-write
n
0x0
0x0
NMI
Non-Maskable Interrupt
0
1
STATUS
Status
0x1
8
read-only
n
0x0
0x0
SYNCBUSY
Synchronization Busy
7
1
read-only
WAKEUP
Wake-Up Enable
0x14
32
read-write
n
0x0
0x0
WAKEUPEN0
External Interrupt 0 Wake-up Enable
0
1
WAKEUPEN1
External Interrupt 1 Wake-up Enable
1
1
WAKEUPEN10
External Interrupt 10 Wake-up Enable
10
1
WAKEUPEN11
External Interrupt 11 Wake-up Enable
11
1
WAKEUPEN12
External Interrupt 12 Wake-up Enable
12
1
WAKEUPEN13
External Interrupt 13 Wake-up Enable
13
1
WAKEUPEN14
External Interrupt 14 Wake-up Enable
14
1
WAKEUPEN15
External Interrupt 15 Wake-up Enable
15
1
WAKEUPEN2
External Interrupt 2 Wake-up Enable
2
1
WAKEUPEN3
External Interrupt 3 Wake-up Enable
3
1
WAKEUPEN4
External Interrupt 4 Wake-up Enable
4
1
WAKEUPEN5
External Interrupt 5 Wake-up Enable
5
1
WAKEUPEN6
External Interrupt 6 Wake-up Enable
6
1
WAKEUPEN7
External Interrupt 7 Wake-up Enable
7
1
WAKEUPEN8
External Interrupt 8 Wake-up Enable
8
1
WAKEUPEN9
External Interrupt 9 Wake-up Enable
9
1
EVSYS
Event System Interface
EVSYS
0x0
0x0
0x1C
registers
n
0x0
0x1C
registers
n
0x0
0x1C
registers
n
0x0
0x1C
registers
n
EVSYS_INTREQ
8
EVSYS
8
CHANNEL
Channel
0x4
32
read-write
n
0x0
0x0
CHANNEL
Channel Selection
0
4
EDGSEL
Edge Detection Selection
26
2
EDGSELSelect
NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
0
RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
1
FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
2
BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
3
EVGEN
Event Generator Selection
16
7
PATH
Path Selection
24
2
PATHSelect
SYNCHRONOUS
Synchronous path
0
RESYNCHRONIZED
Resynchronized path
1
ASYNCHRONOUS
Asynchronous path
2
SWEVT
Software Event
8
1
CHSTATUS
Channel Status
0xC
32
read-only
n
0x0
0x0
CHBUSY0
Channel 0 Busy
8
1
read-only
CHBUSY1
Channel 1 Busy
9
1
read-only
CHBUSY10
Channel 10 Busy
26
1
read-only
CHBUSY11
Channel 11 Busy
27
1
read-only
CHBUSY2
Channel 2 Busy
10
1
read-only
CHBUSY3
Channel 3 Busy
11
1
read-only
CHBUSY4
Channel 4 Busy
12
1
read-only
CHBUSY5
Channel 5 Busy
13
1
read-only
CHBUSY6
Channel 6 Busy
14
1
read-only
CHBUSY7
Channel 7 Busy
15
1
read-only
CHBUSY8
Channel 8 Busy
24
1
read-only
CHBUSY9
Channel 9 Busy
25
1
read-only
USRRDY0
Channel 0 User Ready
0
1
read-only
USRRDY1
Channel 1 User Ready
1
1
read-only
USRRDY10
Channel 10 User Ready
18
1
read-only
USRRDY11
Channel 11 User Ready
19
1
read-only
USRRDY2
Channel 2 User Ready
2
1
read-only
USRRDY3
Channel 3 User Ready
3
1
read-only
USRRDY4
Channel 4 User Ready
4
1
read-only
USRRDY5
Channel 5 User Ready
5
1
read-only
USRRDY6
Channel 6 User Ready
6
1
read-only
USRRDY7
Channel 7 User Ready
7
1
read-only
USRRDY8
Channel 8 User Ready
16
1
read-only
USRRDY9
Channel 9 User Ready
17
1
read-only
CTRL
Control
0x0
8
write-only
n
0x0
0x0
GCLKREQ
Generic Clock Requests
4
1
SWRST
Software Reset
0
1
write-only
INTENCLR
Interrupt Enable Clear
0x10
32
read-write
n
0x0
0x0
EVD0
Channel 0 Event Detection Interrupt Enable
8
1
EVD1
Channel 1 Event Detection Interrupt Enable
9
1
EVD10
Channel 10 Event Detection Interrupt Enable
26
1
EVD11
Channel 11 Event Detection Interrupt Enable
27
1
EVD2
Channel 2 Event Detection Interrupt Enable
10
1
EVD3
Channel 3 Event Detection Interrupt Enable
11
1
EVD4
Channel 4 Event Detection Interrupt Enable
12
1
EVD5
Channel 5 Event Detection Interrupt Enable
13
1
EVD6
Channel 6 Event Detection Interrupt Enable
14
1
EVD7
Channel 7 Event Detection Interrupt Enable
15
1
EVD8
Channel 8 Event Detection Interrupt Enable
24
1
EVD9
Channel 9 Event Detection Interrupt Enable
25
1
OVR0
Channel 0 Overrun Interrupt Enable
0
1
OVR1
Channel 1 Overrun Interrupt Enable
1
1
OVR10
Channel 10 Overrun Interrupt Enable
18
1
OVR11
Channel 11 Overrun Interrupt Enable
19
1
OVR2
Channel 2 Overrun Interrupt Enable
2
1
OVR3
Channel 3 Overrun Interrupt Enable
3
1
OVR4
Channel 4 Overrun Interrupt Enable
4
1
OVR5
Channel 5 Overrun Interrupt Enable
5
1
OVR6
Channel 6 Overrun Interrupt Enable
6
1
OVR7
Channel 7 Overrun Interrupt Enable
7
1
OVR8
Channel 8 Overrun Interrupt Enable
16
1
OVR9
Channel 9 Overrun Interrupt Enable
17
1
INTENSET
Interrupt Enable Set
0x14
32
read-write
n
0x0
0x0
EVD0
Channel 0 Event Detection Interrupt Enable
8
1
EVD1
Channel 1 Event Detection Interrupt Enable
9
1
EVD10
Channel 10 Event Detection Interrupt Enable
26
1
EVD11
Channel 11 Event Detection Interrupt Enable
27
1
EVD2
Channel 2 Event Detection Interrupt Enable
10
1
EVD3
Channel 3 Event Detection Interrupt Enable
11
1
EVD4
Channel 4 Event Detection Interrupt Enable
12
1
EVD5
Channel 5 Event Detection Interrupt Enable
13
1
EVD6
Channel 6 Event Detection Interrupt Enable
14
1
EVD7
Channel 7 Event Detection Interrupt Enable
15
1
EVD8
Channel 8 Event Detection Interrupt Enable
24
1
EVD9
Channel 9 Event Detection Interrupt Enable
25
1
OVR0
Channel 0 Overrun Interrupt Enable
0
1
OVR1
Channel 1 Overrun Interrupt Enable
1
1
OVR10
Channel 10 Overrun Interrupt Enable
18
1
OVR11
Channel 11 Overrun Interrupt Enable
19
1
OVR2
Channel 2 Overrun Interrupt Enable
2
1
OVR3
Channel 3 Overrun Interrupt Enable
3
1
OVR4
Channel 4 Overrun Interrupt Enable
4
1
OVR5
Channel 5 Overrun Interrupt Enable
5
1
OVR6
Channel 6 Overrun Interrupt Enable
6
1
OVR7
Channel 7 Overrun Interrupt Enable
7
1
OVR8
Channel 8 Overrun Interrupt Enable
16
1
OVR9
Channel 9 Overrun Interrupt Enable
17
1
INTFLAG
Interrupt Flag Status and Clear
0x18
32
read-write
n
0x0
0x0
EVD0
Channel 0 Event Detection
8
1
EVD1
Channel 1 Event Detection
9
1
EVD10
Channel 10 Event Detection
26
1
EVD11
Channel 11 Event Detection
27
1
EVD2
Channel 2 Event Detection
10
1
EVD3
Channel 3 Event Detection
11
1
EVD4
Channel 4 Event Detection
12
1
EVD5
Channel 5 Event Detection
13
1
EVD6
Channel 6 Event Detection
14
1
EVD7
Channel 7 Event Detection
15
1
EVD8
Channel 8 Event Detection
24
1
EVD9
Channel 9 Event Detection
25
1
OVR0
Channel 0 Overrun
0
1
OVR1
Channel 1 Overrun
1
1
OVR10
Channel 10 Overrun
18
1
OVR11
Channel 11 Overrun
19
1
OVR2
Channel 2 Overrun
2
1
OVR3
Channel 3 Overrun
3
1
OVR4
Channel 4 Overrun
4
1
OVR5
Channel 5 Overrun
5
1
OVR6
Channel 6 Overrun
6
1
OVR7
Channel 7 Overrun
7
1
OVR8
Channel 8 Overrun
16
1
OVR9
Channel 9 Overrun
17
1
USER
User Multiplexer
0x8
16
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
8
5
CHANNELSelect
0
No Channel Output Selected
0
USER
User Multiplexer Selection
0
5
GCLK
Generic Clock Generator
GCLK
0x0
0x0
0xC
registers
n
0x0
0xC
registers
n
0x0
0xC
registers
n
0x0
0xC
registers
n
CLKCTRL
Generic Clock Control
0x2
16
read-write
n
0x0
0x0
CLKEN
Clock Enable
14
1
GEN
Generic Clock Generator
8
4
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
GCLK5
Generic clock generator 5
0x5
GCLK6
Generic clock generator 6
0x6
GCLK7
Generic clock generator 7
0x7
GCLK8
Generic clock generator 8
0x8
ID
Generic Clock Selection ID
0
6
IDSelect
DFLL48
DFLL48
0x0
FDPLL
FDPLL
0x1
EVSYS_9
EVSYS_9
0x10
EVSYS_10
EVSYS_10
0x11
EVSYS_11
EVSYS_11
0x12
SERCOMX_SLOW
SERCOMX_SLOW
0x13
SERCOM0_CORE
SERCOM0_CORE
0x14
SERCOM1_CORE
SERCOM1_CORE
0x15
SERCOM2_CORE
SERCOM2_CORE
0x16
SERCOM3_CORE
SERCOM3_CORE
0x17
SERCOM4_CORE
SERCOM4_CORE
0x18
SERCOM5_CORE
SERCOM5_CORE
0x19
TCC0_TCC1
TCC0_TCC1
0x1A
TCC2_TC3
TCC2_TC3
0x1B
TC4_TC5
TC4_TC5
0x1C
TC6_TC7
TC6_TC7
0x1D
ADC
ADC
0x1E
AC_DIG
AC_DIG
0x1F
FDPLL32K
FDPLL32K
0x2
AC_ANA
AC_ANA
0x20
DAC
DAC
0x21
I2S_0
I2S_0
0x23
I2S_1
I2S_1
0x24
WDT
WDT
0x3
RTC
RTC
0x4
EIC
EIC
0x5
USB
USB
0x6
EVSYS_0
EVSYS_0
0x7
EVSYS_1
EVSYS_1
0x8
EVSYS_2
EVSYS_2
0x9
EVSYS_3
EVSYS_3
0xA
EVSYS_4
EVSYS_4
0xB
EVSYS_5
EVSYS_5
0xC
EVSYS_6
EVSYS_6
0xD
EVSYS_7
EVSYS_7
0xE
EVSYS_8
EVSYS_8
0xF
WRTLOCK
Write Lock
15
1
CTRL
Control
0x0
8
read-write
n
0x0
0x0
SWRST
Software Reset
0
1
GENCTRL
Generic Clock Generator Control
0x4
32
read-write
n
0x0
0x0
DIVSEL
Divide Selection
20
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
16
1
ID
Generic Clock Generator Selection
0
4
IDC
Improve Duty Cycle
17
1
OE
Output Enable
19
1
OOV
Output Off Value
18
1
RUNSTDBY
Run in Standby
21
1
SRC
Source Select
8
5
SRCSelect
XOSC
XOSC oscillator output
0
FDPLL
FDPLL output
0x8
GCLKIN
Generator input pad
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
OSC32K
OSC32K oscillator output
4
XOSC32K
XOSC32K oscillator output
5
OSC8M
OSC8M oscillator output
6
DFLL48M
DFLL48M output
7
DPLL96M
DPLL96M output
8
GENDIV
Generic Clock Generator Division
0x8
32
read-write
n
0x0
0x0
DIV
Division Factor
8
16
ID
Generic Clock Generator Selection
0
4
STATUS
Status
0x1
8
read-only
n
0x0
0x0
SYNCBUSY
Synchronization Busy Status
7
1
read-only
HMATRIX
HSB Matrix
HMATRIXB
0x0
0x0
0x400
registers
n
PRAS0
Priority A for Slave
0x80
32
read-write
n
0x0
0x0
PRAS1
Priority A for Slave
0x88
32
read-write
n
0x0
0x0
PRAS10
Priority A for Slave
0xD0
32
read-write
n
0x0
0x0
PRAS11
Priority A for Slave
0xD8
32
read-write
n
0x0
0x0
PRAS12
Priority A for Slave
0xE0
32
read-write
n
0x0
0x0
PRAS13
Priority A for Slave
0xE8
32
read-write
n
0x0
0x0
PRAS14
Priority A for Slave
0xF0
32
read-write
n
0x0
0x0
PRAS15
Priority A for Slave
0xF8
32
read-write
n
0x0
0x0
PRAS2
Priority A for Slave
0x90
32
read-write
n
0x0
0x0
PRAS3
Priority A for Slave
0x98
32
read-write
n
0x0
0x0
PRAS4
Priority A for Slave
0xA0
32
read-write
n
0x0
0x0
PRAS5
Priority A for Slave
0xA8
32
read-write
n
0x0
0x0
PRAS6
Priority A for Slave
0xB0
32
read-write
n
0x0
0x0
PRAS7
Priority A for Slave
0xB8
32
read-write
n
0x0
0x0
PRAS8
Priority A for Slave
0xC0
32
read-write
n
0x0
0x0
PRAS9
Priority A for Slave
0xC8
32
read-write
n
0x0
0x0
PRBS0
Priority B for Slave
0x84
32
read-write
n
0x0
0x0
PRBS1
Priority B for Slave
0x8C
32
read-write
n
0x0
0x0
PRBS10
Priority B for Slave
0xD4
32
read-write
n
0x0
0x0
PRBS11
Priority B for Slave
0xDC
32
read-write
n
0x0
0x0
PRBS12
Priority B for Slave
0xE4
32
read-write
n
0x0
0x0
PRBS13
Priority B for Slave
0xEC
32
read-write
n
0x0
0x0
PRBS14
Priority B for Slave
0xF4
32
read-write
n
0x0
0x0
PRBS15
Priority B for Slave
0xFC
32
read-write
n
0x0
0x0
PRBS2
Priority B for Slave
0x94
32
read-write
n
0x0
0x0
PRBS3
Priority B for Slave
0x9C
32
read-write
n
0x0
0x0
PRBS4
Priority B for Slave
0xA4
32
read-write
n
0x0
0x0
PRBS5
Priority B for Slave
0xAC
32
read-write
n
0x0
0x0
PRBS6
Priority B for Slave
0xB4
32
read-write
n
0x0
0x0
PRBS7
Priority B for Slave
0xBC
32
read-write
n
0x0
0x0
PRBS8
Priority B for Slave
0xC4
32
read-write
n
0x0
0x0
PRBS9
Priority B for Slave
0xCC
32
read-write
n
0x0
0x0
SFR0
Special Function
0x110
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR1
Special Function
0x114
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR10
Special Function
0x138
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR11
Special Function
0x13C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR12
Special Function
0x140
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR13
Special Function
0x144
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR14
Special Function
0x148
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR15
Special Function
0x14C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR2
Special Function
0x118
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR3
Special Function
0x11C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR4
Special Function
0x120
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR5
Special Function
0x124
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR6
Special Function
0x128
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR7
Special Function
0x12C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR8
Special Function
0x130
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR9
Special Function
0x134
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
I2S
Inter-IC Sound Interface
I2S
0x0
0x0
0x38
registers
n
0x0
0x38
registers
n
0x0
0x38
registers
n
0x0
0x38
registers
n
I2S_INTREQ
27
I2S
27
CLKCTRL0
Clock Unit n Control
0x4
32
read-write
n
0x0
0x0
BITDELAY
Data Delay from Frame Sync
7
1
BITDELAYSelect
LJ
Left Justified (0 Bit Delay)
0x0
I2S
I2S (1 Bit Delay)
0x1
FSINV
Frame Sync Invert
11
1
FSOUTINV
Frame Sync Output Invert
29
1
FSSEL
Frame Sync Select
8
1
FSSELSelect
SCKDIV
Divided Serial Clock n is used as Frame Sync n source
0x0
FSPIN
FSn input pin is used as Frame Sync n source
0x1
FSWIDTH
Frame Sync Width
5
2
FSWIDTHSelect
SLOT
Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
0x0
HALF
Frame Sync Pulse is half a Frame wide
0x1
BIT
Frame Sync Pulse is 1 Bit wide
0x2
BURST
Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
0x3
MCKDIV
Master Clock Division Factor
19
5
MCKEN
Master Clock Enable
18
1
MCKOUTDIV
Master Clock Output Division Factor
24
5
MCKOUTINV
Master Clock Output Invert
31
1
MCKSEL
Master Clock Select
16
1
MCKSELSelect
GCLK
GCLK_I2S_n is used as Master Clock n source
0x0
MCKPIN
MCKn input pin is used as Master Clock n source
0x1
NBSLOTS
Number of Slots in Frame
2
3
SCKOUTINV
Serial Clock Output Invert
30
1
SCKSEL
Serial Clock Select
12
1
SCKSELSelect
MCKDIV
Divided Master Clock n is used as Serial Clock n source
0x0
SCKPIN
SCKn input pin is used as Serial Clock n source
0x1
SLOTSIZE
Slot Size
0
2
SLOTSIZESelect
8
8-bit Slot for Clock Unit n
0x0
16
16-bit Slot for Clock Unit n
0x1
24
24-bit Slot for Clock Unit n
0x2
32
32-bit Slot for Clock Unit n
0x3
CLKCTRL1
Clock Unit n Control
0x8
32
read-write
n
0x0
0x0
BITDELAY
Data Delay from Frame Sync
7
1
BITDELAYSelect
LJ
Left Justified (0 Bit Delay)
0x0
I2S
I2S (1 Bit Delay)
0x1
FSINV
Frame Sync Invert
11
1
FSOUTINV
Frame Sync Output Invert
29
1
FSSEL
Frame Sync Select
8
1
FSSELSelect
SCKDIV
Divided Serial Clock n is used as Frame Sync n source
0x0
FSPIN
FSn input pin is used as Frame Sync n source
0x1
FSWIDTH
Frame Sync Width
5
2
FSWIDTHSelect
SLOT
Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
0x0
HALF
Frame Sync Pulse is half a Frame wide
0x1
BIT
Frame Sync Pulse is 1 Bit wide
0x2
BURST
Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
0x3
MCKDIV
Master Clock Division Factor
19
5
MCKEN
Master Clock Enable
18
1
MCKOUTDIV
Master Clock Output Division Factor
24
5
MCKOUTINV
Master Clock Output Invert
31
1
MCKSEL
Master Clock Select
16
1
MCKSELSelect
GCLK
GCLK_I2S_n is used as Master Clock n source
0x0
MCKPIN
MCKn input pin is used as Master Clock n source
0x1
NBSLOTS
Number of Slots in Frame
2
3
SCKOUTINV
Serial Clock Output Invert
30
1
SCKSEL
Serial Clock Select
12
1
SCKSELSelect
MCKDIV
Divided Master Clock n is used as Serial Clock n source
0x0
SCKPIN
SCKn input pin is used as Serial Clock n source
0x1
SLOTSIZE
Slot Size
0
2
SLOTSIZESelect
8
8-bit Slot for Clock Unit n
0x0
16
16-bit Slot for Clock Unit n
0x1
24
24-bit Slot for Clock Unit n
0x2
32
32-bit Slot for Clock Unit n
0x3
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
CKEN0
Clock Unit 0 Enable
2
1
CKEN1
Clock Unit 1 Enable
3
1
ENABLE
Enable
1
1
SEREN0
Serializer 0 Enable
4
1
SEREN1
Serializer 1 Enable
5
1
SWRST
Software Reset
0
1
DATA0
Data n
0x30
32
read-write
n
0x0
0x0
DATA
Sample Data
0
32
DATA1
Data n
0x34
32
read-write
n
0x0
0x0
DATA
Sample Data
0
32
INTENCLR
Interrupt Enable Clear
0xC
16
read-write
n
0x0
0x0
RXOR0
Receive Overrun 0 Interrupt Enable
4
1
RXOR1
Receive Overrun 1 Interrupt Enable
5
1
RXRDY0
Receive Ready 0 Interrupt Enable
0
1
RXRDY1
Receive Ready 1 Interrupt Enable
1
1
TXRDY0
Transmit Ready 0 Interrupt Enable
8
1
TXRDY1
Transmit Ready 1 Interrupt Enable
9
1
TXUR0
Transmit Underrun 0 Interrupt Enable
12
1
TXUR1
Transmit Underrun 1 Interrupt Enable
13
1
INTENSET
Interrupt Enable Set
0x10
16
read-write
n
0x0
0x0
RXOR0
Receive Overrun 0 Interrupt Enable
4
1
RXOR1
Receive Overrun 1 Interrupt Enable
5
1
RXRDY0
Receive Ready 0 Interrupt Enable
0
1
RXRDY1
Receive Ready 1 Interrupt Enable
1
1
TXRDY0
Transmit Ready 0 Interrupt Enable
8
1
TXRDY1
Transmit Ready 1 Interrupt Enable
9
1
TXUR0
Transmit Underrun 0 Interrupt Enable
12
1
TXUR1
Transmit Underrun 1 Interrupt Enable
13
1
INTFLAG
Interrupt Flag Status and Clear
0x14
16
read-write
n
0x0
0x0
RXOR0
Receive Overrun 0
4
1
RXOR1
Receive Overrun 1
5
1
RXRDY0
Receive Ready 0
0
1
RXRDY1
Receive Ready 1
1
1
TXRDY0
Transmit Ready 0
8
1
TXRDY1
Transmit Ready 1
9
1
TXUR0
Transmit Underrun 0
12
1
TXUR1
Transmit Underrun 1
13
1
SERCTRL0
Serializer n Control
0x20
32
read-write
n
0x0
0x0
BITREV
Data Formatting Bit Reverse
15
1
BITREVSelect
MSBIT
Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
0x0
LSBIT
Transfer Data Least Significant Bit (LSB) first
0x1
CLKSEL
Clock Unit Selection
5
1
CLKSELSelect
CLK0
Use Clock Unit 0
0x0
CLK1
Use Clock Unit 1
0x1
DATASIZE
Data Word Size
8
3
DATASIZESelect
32
32 bits
0x0
24
24 bits
0x1
20
20 bits
0x2
18
18 bits
0x3
16
16 bits
0x4
16C
16 bits compact stereo
0x5
8
8 bits
0x6
8C
8 bits compact stereo
0x7
DMA
Single or Multiple DMA Channels
25
1
DMASelect
SINGLE
Single DMA channel
0x0
MULTIPLE
One DMA channel per data channel
0x1
EXTEND
Data Formatting Bit Extension
13
2
EXTENDSelect
ZERO
Extend with zeroes
0x0
ONE
Extend with ones
0x1
MSBIT
Extend with Most Significant Bit
0x2
LSBIT
Extend with Least Significant Bit
0x3
MONO
Mono Mode
24
1
MONOSelect
STEREO
Normal mode
0x0
MONO
Left channel data is duplicated to right channel
0x1
RXLOOP
Loop-back Test Mode
26
1
SERMODE
Serializer Mode
0
2
SERMODESelect
RX
Receive
0x0
TX
Transmit
0x1
PDM2
Receive one PDM data on each serial clock edge
0x2
SLOTADJ
Data Slot Formatting Adjust
7
1
SLOTADJSelect
RIGHT
Data is right adjusted in slot
0x0
LEFT
Data is left adjusted in slot
0x1
SLOTDIS0
Slot 0 Disabled for this Serializer
16
1
SLOTDIS1
Slot 1 Disabled for this Serializer
17
1
SLOTDIS2
Slot 2 Disabled for this Serializer
18
1
SLOTDIS3
Slot 3 Disabled for this Serializer
19
1
SLOTDIS4
Slot 4 Disabled for this Serializer
20
1
SLOTDIS5
Slot 5 Disabled for this Serializer
21
1
SLOTDIS6
Slot 6 Disabled for this Serializer
22
1
SLOTDIS7
Slot 7 Disabled for this Serializer
23
1
TXDEFAULT
Line Default Line when Slot Disabled
2
2
TXDEFAULTSelect
ZERO
Output Default Value is 0
0x0
ONE
Output Default Value is 1
0x1
HIZ
Output Default Value is high impedance
0x3
TXSAME
Transmit Data when Underrun
4
1
TXSAMESelect
ZERO
Zero data transmitted in case of underrun
0x0
SAME
Last data transmitted in case of underrun
0x1
WORDADJ
Data Word Formatting Adjust
12
1
WORDADJSelect
RIGHT
Data is right adjusted in word
0x0
LEFT
Data is left adjusted in word
0x1
SERCTRL1
Serializer n Control
0x24
32
read-write
n
0x0
0x0
BITREV
Data Formatting Bit Reverse
15
1
BITREVSelect
MSBIT
Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
0x0
LSBIT
Transfer Data Least Significant Bit (LSB) first
0x1
CLKSEL
Clock Unit Selection
5
1
CLKSELSelect
CLK0
Use Clock Unit 0
0x0
CLK1
Use Clock Unit 1
0x1
DATASIZE
Data Word Size
8
3
DATASIZESelect
32
32 bits
0x0
24
24 bits
0x1
20
20 bits
0x2
18
18 bits
0x3
16
16 bits
0x4
16C
16 bits compact stereo
0x5
8
8 bits
0x6
8C
8 bits compact stereo
0x7
DMA
Single or Multiple DMA Channels
25
1
DMASelect
SINGLE
Single DMA channel
0x0
MULTIPLE
One DMA channel per data channel
0x1
EXTEND
Data Formatting Bit Extension
13
2
EXTENDSelect
ZERO
Extend with zeroes
0x0
ONE
Extend with ones
0x1
MSBIT
Extend with Most Significant Bit
0x2
LSBIT
Extend with Least Significant Bit
0x3
MONO
Mono Mode
24
1
MONOSelect
STEREO
Normal mode
0x0
MONO
Left channel data is duplicated to right channel
0x1
RXLOOP
Loop-back Test Mode
26
1
SERMODE
Serializer Mode
0
2
SERMODESelect
RX
Receive
0x0
TX
Transmit
0x1
PDM2
Receive one PDM data on each serial clock edge
0x2
SLOTADJ
Data Slot Formatting Adjust
7
1
SLOTADJSelect
RIGHT
Data is right adjusted in slot
0x0
LEFT
Data is left adjusted in slot
0x1
SLOTDIS0
Slot 0 Disabled for this Serializer
16
1
SLOTDIS1
Slot 1 Disabled for this Serializer
17
1
SLOTDIS2
Slot 2 Disabled for this Serializer
18
1
SLOTDIS3
Slot 3 Disabled for this Serializer
19
1
SLOTDIS4
Slot 4 Disabled for this Serializer
20
1
SLOTDIS5
Slot 5 Disabled for this Serializer
21
1
SLOTDIS6
Slot 6 Disabled for this Serializer
22
1
SLOTDIS7
Slot 7 Disabled for this Serializer
23
1
TXDEFAULT
Line Default Line when Slot Disabled
2
2
TXDEFAULTSelect
ZERO
Output Default Value is 0
0x0
ONE
Output Default Value is 1
0x1
HIZ
Output Default Value is high impedance
0x3
TXSAME
Transmit Data when Underrun
4
1
TXSAMESelect
ZERO
Zero data transmitted in case of underrun
0x0
SAME
Last data transmitted in case of underrun
0x1
WORDADJ
Data Word Formatting Adjust
12
1
WORDADJSelect
RIGHT
Data is right adjusted in word
0x0
LEFT
Data is left adjusted in word
0x1
SYNCBUSY
Synchronization Status
0x18
16
read-only
n
0x0
0x0
CKEN0
Clock Unit 0 Enable Synchronization Status
2
1
CKEN1
Clock Unit 1 Enable Synchronization Status
3
1
DATA0
Data 0 Synchronization Status
8
1
DATA1
Data 1 Synchronization Status
9
1
ENABLE
Enable Synchronization Status
1
1
SEREN0
Serializer 0 Enable Synchronization Status
4
1
SEREN1
Serializer 1 Enable Synchronization Status
5
1
SWRST
Software Reset Synchronization Status
0
1
MTB
Cortex-M0+ Micro-Trace Buffer
MTB
0x0
0x0
0x1000
registers
n
AUTHSTATUS
MTB Authentication Status
0xFB8
32
read-only
n
0x0
0x0
BASE
MTB Base
0xC
32
read-only
n
0x0
0x0
CID0
CoreSight
0xFF0
32
read-only
n
0x0
0x0
CID1
CoreSight
0xFF4
32
read-only
n
0x0
0x0
CID2
CoreSight
0xFF8
32
read-only
n
0x0
0x0
CID3
CoreSight
0xFFC
32
read-only
n
0x0
0x0
CLAIMCLR
MTB Claim Clear
0xFA4
32
read-write
n
0x0
0x0
CLAIMSET
MTB Claim Set
0xFA0
32
read-write
n
0x0
0x0
DEVARCH
MTB Device Architecture
0xFBC
32
read-only
n
0x0
0x0
DEVID
MTB Device Configuration
0xFC8
32
read-only
n
0x0
0x0
DEVTYPE
MTB Device Type
0xFCC
32
read-only
n
0x0
0x0
FLOW
MTB Flow
0x8
32
read-write
n
0x0
0x0
AUTOHALT
Auto Halt Request
1
1
AUTOSTOP
Auto Stop Tracing
0
1
WATERMARK
Watermark value
3
29
ITCTRL
MTB Integration Mode Control
0xF00
32
read-write
n
0x0
0x0
LOCKACCESS
MTB Lock Access
0xFB0
32
read-write
n
0x0
0x0
LOCKSTATUS
MTB Lock Status
0xFB4
32
read-only
n
0x0
0x0
MASTER
MTB Master
0x4
32
read-write
n
0x0
0x0
EN
Main Trace Enable
31
1
HALTREQ
Halt Request
9
1
MASK
Maximum Value of the Trace Buffer in SRAM
0
5
RAMPRIV
SRAM Privilege
8
1
SFRWPRIV
Special Function Register Write Privilege
7
1
TSTARTEN
Trace Start Input Enable
5
1
TSTOPEN
Trace Stop Input Enable
6
1
PID0
CoreSight
0xFE0
32
read-only
n
0x0
0x0
PID1
CoreSight
0xFE4
32
read-only
n
0x0
0x0
PID2
CoreSight
0xFE8
32
read-only
n
0x0
0x0
PID3
CoreSight
0xFEC
32
read-only
n
0x0
0x0
PID4
CoreSight
0xFD0
32
read-only
n
0x0
0x0
PID5
CoreSight
0xFD4
32
read-only
n
0x0
0x0
PID6
CoreSight
0xFD8
32
read-only
n
0x0
0x0
PID7
CoreSight
0xFDC
32
read-only
n
0x0
0x0
POSITION
MTB Position
0x0
32
read-write
n
0x0
0x0
POINTER
Trace Packet Location Pointer
3
29
WRAP
Pointer Value Wraps
2
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x320
registers
n
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
Interrupt clear-enable bits
0
29
ICPR
Interrupt Clear Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
Interrupt clear-pending bits
0
29
IPR0
Interrupt Priority Register n
0x300
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR1
Interrupt Priority Register n
0x304
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR2
Interrupt Priority Register n
0x308
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR3
Interrupt Priority Register n
0x30C
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR4
Interrupt Priority Register n
0x310
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR5
Interrupt Priority Register n
0x314
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR6
Interrupt Priority Register n
0x318
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
IPR7
Interrupt Priority Register n
0x31C
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
Interrupt set enable bits
0
29
ISPR
Interrupt Set Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
Interrupt set-pending bits
0
29
NVMCTRL
Non-Volatile Memory Controller
NVMCTRL
0x0
0x0
0x22
registers
n
0x0
0x22
registers
n
0x0
0x22
registers
n
0x0
0x22
registers
n
NVMCTRL_INTREQ
5
NVMCTRL
5
ADDR
Address
0x1C
32
read-write
n
0x0
0x0
ADDR
NVM Address
0
22
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
CMD
Command
0
7
CMDSelect
ER
Erase Row - Erases the row addressed by the ADDR register.
0x02
WP
Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x04
EAR
Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
0x05
WAP
Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
0x06
SF
Security Flow Command
0x0A
WL
Write lockbits
0x0F
RWWEEER
RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register.
0x1A
RWWEEWP
RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x1C
LR
Lock Region - Locks the region containing the address location in the ADDR register.
0x40
UR
Unlock Region - Unlocks the region containing the address location in the ADDR register.
0x41
SPRM
Sets the power reduction mode.
0x42
CPRM
Clears the power reduction mode.
0x43
PBC
Page Buffer Clear - Clears the page buffer.
0x44
SSB
Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
0x45
INVALL
Invalidate all cache lines.
0x46
CMDEX
Command Execution
8
8
CMDEXSelect
KEY
Execution Key
0xA5
CTRLB
Control B
0x4
32
read-write
n
0x0
0x0
CACHEDIS
Cache Disable
18
1
MANW
Manual Write
7
1
READMODE
NVMCTRL Read Mode
16
2
READMODESelect
NO_MISS_PENALTY
The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
0x0
LOW_POWER
Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
0x1
DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
0x2
RWS
NVM Read Wait States
1
4
RWSSelect
SINGLE
Single Auto Wait State
0
HALF
Half Auto Wait State
1
DUAL
Dual Auto Wait State
2
SLEEPPRM
Power Reduction Mode during Sleep
8
2
SLEEPPRMSelect
WAKEONACCESS
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
0
WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
1
DISABLED
Auto power reduction disabled.
3
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERROR
Error Interrupt Enable
1
1
READY
NVM Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x10
8
read-write
n
0x0
0x0
ERROR
Error Interrupt Enable
1
1
READY
NVM Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x14
8
read-write
n
0x0
0x0
ERROR
Error
1
1
READY
NVM Ready
0
1
LOCK
Lock Section
0x20
16
read-write
n
0x0
0x0
LOCK
Region Lock Bits
0
16
read-only
PARAM
NVM Parameter
0x8
32
read-write
n
0x0
0x0
NVMP
NVM Pages
0
16
read-only
PSZ
Page Size
16
3
read-only
PSZSelect
8
8 bytes
0x0
16
16 bytes
0x1
32
32 bytes
0x2
64
64 bytes
0x3
128
128 bytes
0x4
256
256 bytes
0x5
512
512 bytes
0x6
1024
1024 bytes
0x7
RWWEEP
RWW EEPROM Pages
20
12
read-only
STATUS
Status
0x18
16
read-write
n
0x0
0x0
LOAD
NVM Page Buffer Active Loading
1
1
LOCKE
Lock Error Status
3
1
NVME
NVM Error
4
1
PRM
Power Reduction Mode
0
1
read-only
PROGE
Programming Error Status
2
1
SB
Security Bit Status
8
1
read-only
PAC0
Peripheral Access Controller
PAC
0x0
0x0
0x8
registers
n
WPCLR
Write Protection Clear
0x0
32
read-write
n
0x0
0x0
WP
Write Protection Clear
1
31
WPSET
Write Protection Set
0x4
32
read-write
n
0x0
0x0
WP
Write Protection Set
1
31
PAC1
Peripheral Access Controller
PAC
0x0
0x0
0x8
registers
n
WPCLR
Write Protection Clear
0x0
32
read-write
n
0x0
0x0
WP
Write Protection Clear
1
31
WPSET
Write Protection Set
0x4
32
read-write
n
0x0
0x0
WP
Write Protection Set
1
31
PAC2
Peripheral Access Controller
PAC
0x0
0x0
0x8
registers
n
WPCLR
Write Protection Clear
0x0
32
read-write
n
0x0
0x0
WP
Write Protection Clear
1
31
WPSET
Write Protection Set
0x4
32
read-write
n
0x0
0x0
WP
Write Protection Set
1
31
PM
Power Manager
PM
0x0
0x0
0x39
registers
n
0x0
0x39
registers
n
0x0
0x39
registers
n
0x0
0x39
registers
n
PM_INTREQ
0
PM
0
AHBMASK
AHB Mask
0x14
32
read-write
n
0x0
0x0
DMAC_
DMAC AHB Clock Mask
5
1
DSU_
DSU AHB Clock Mask
3
1
HPB0_
HPB0 AHB Clock Mask
0
1
HPB1_
HPB1 AHB Clock Mask
1
1
HPB2_
HPB2 AHB Clock Mask
2
1
NVMCTRL_
NVMCTRL AHB Clock Mask
4
1
USB_
USB AHB Clock Mask
6
1
APBAMASK
APBA Mask
0x18
32
read-write
n
0x0
0x0
EIC_
EIC APB Clock Enable
6
1
GCLK_
GCLK APB Clock Enable
3
1
PAC0_
PAC0 APB Clock Enable
0
1
PM_
PM APB Clock Enable
1
1
RTC_
RTC APB Clock Enable
5
1
SYSCTRL_
SYSCTRL APB Clock Enable
2
1
WDT_
WDT APB Clock Enable
4
1
APBASEL
APBA Clock Select
0x9
8
read-write
n
0x0
0x0
APBADIV
APBA Prescaler Selection
0
3
APBADIVSelect
DIV1
Divide by 1
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV32
Divide by 32
5
DIV64
Divide by 64
6
DIV128
Divide by 128
7
APBBMASK
APBB Mask
0x1C
32
read-write
n
0x0
0x0
DMAC_
DMAC APB Clock Enable
4
1
DSU_
DSU APB Clock Enable
1
1
HMATRIX_
HMATRIX APB Clock Enable
6
1
NVMCTRL_
NVMCTRL APB Clock Enable
2
1
PAC1_
PAC1 APB Clock Enable
0
1
PORT_
PORT APB Clock Enable
3
1
USB_
USB APB Clock Enable
5
1
APBBSEL
APBB Clock Select
0xA
8
read-write
n
0x0
0x0
APBBDIV
APBB Prescaler Selection
0
3
APBBDIVSelect
DIV1
Divide by 1
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV32
Divide by 32
5
DIV64
Divide by 64
6
DIV128
Divide by 128
7
APBCMASK
APBC Mask
0x20
32
read-write
n
0x0
0x0
AC_
AC APB Clock Enable
17
1
ADC_
ADC APB Clock Enable
16
1
DAC_
DAC APB Clock Enable
18
1
EVSYS_
EVSYS APB Clock Enable
1
1
I2S_
I2S APB Clock Enable
20
1
PAC2_
PAC2 APB Clock Enable
0
1
PTC_
PTC APB Clock Enable
19
1
SERCOM0_
SERCOM0 APB Clock Enable
2
1
SERCOM1_
SERCOM1 APB Clock Enable
3
1
SERCOM2_
SERCOM2 APB Clock Enable
4
1
SERCOM3_
SERCOM3 APB Clock Enable
5
1
SERCOM4_
SERCOM4 APB Clock Enable
6
1
SERCOM5_
SERCOM5 APB Clock Enable
7
1
TC3_
TC3 APB Clock Enable
11
1
TC4_
TC4 APB Clock Enable
12
1
TC5_
TC5 APB Clock Enable
13
1
TC6_
TC6 APB Clock Enable
14
1
TC7_
TC7 APB Clock Enable
15
1
TCC0_
TCC0 APB Clock Enable
8
1
TCC1_
TCC1 APB Clock Enable
9
1
TCC2_
TCC2 APB Clock Enable
10
1
APBCSEL
APBC Clock Select
0xB
8
read-write
n
0x0
0x0
APBCDIV
APBC Prescaler Selection
0
3
APBCDIVSelect
DIV1
Divide by 1
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV32
Divide by 32
5
DIV64
Divide by 64
6
DIV128
Divide by 128
7
CPUSEL
CPU Clock Select
0x8
8
read-write
n
0x0
0x0
CPUDIV
CPU Prescaler Selection
0
3
CPUDIVSelect
DIV1
Divide by 1
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV32
Divide by 32
5
DIV64
Divide by 64
6
DIV128
Divide by 128
7
CTRL
Control
0x0
8
read-write
n
0x0
0x0
EXTCTRL
External Reset Controller
0x2
8
read-write
n
0x0
0x0
SETDIS
External Reset Disable
0
1
INTENCLR
Interrupt Enable Clear
0x34
8
read-write
n
0x0
0x0
CKRDY
Clock Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x35
8
read-write
n
0x0
0x0
CKRDY
Clock Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x36
8
read-write
n
0x0
0x0
CKRDY
Clock Ready
0
1
RCAUSE
Reset Cause
0x38
8
read-only
n
0x0
0x0
BOD12
Brown Out 12 Detector Reset
1
1
BOD33
Brown Out 33 Detector Reset
2
1
EXT
External Reset
4
1
POR
Power On Reset
0
1
SYST
System Reset Request
6
1
WDT
Watchdog Reset
5
1
SLEEP
Sleep Mode
0x1
8
read-write
n
0x0
0x0
IDLE
Idle Mode Configuration
0
2
IDLESelect
CPU
The CPU clock domain is stopped
0
AHB
The CPU and AHB clock domains are stopped
1
APB
The CPU, AHB and APB clock domains are stopped
2
PORT
Port Module
PORT
0x0
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
CTRL
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
CTRL1
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
write-only
DIR
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIR1
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIRCLR
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRCLR1
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRSET
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRSET1
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRTGL
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
DIRTGL1
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
IN
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
Port Data Input Value
0
32
IN1
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
Port Data Input Value
0
32
OUT
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
Port Data Output Value
0
32
OUT1
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
Port Data Output Value
0
32
OUTCLR
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
Port Data Output Value Clear
0
32
OUTCLR1
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
Port Data Output Value Clear
0
32
OUTSET
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
Port Data Output Value Set
0
32
OUTSET1
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
Port Data Output Value Set
0
32
OUTTGL
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
Port Data Output Value Toggle
0
32
OUTTGL1
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
Port Data Output Value Toggle
0
32
PINCFG0
Pin Configuration n
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_0
Pin Configuration n - Group 0
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_1
Pin Configuration n - Group 0
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_10
Pin Configuration n - Group 0
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_11
Pin Configuration n - Group 0
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_12
Pin Configuration n - Group 0
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_13
Pin Configuration n - Group 0
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_14
Pin Configuration n - Group 0
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_15
Pin Configuration n - Group 0
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_16
Pin Configuration n - Group 0
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_17
Pin Configuration n - Group 0
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_18
Pin Configuration n - Group 0
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_19
Pin Configuration n - Group 0
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_2
Pin Configuration n - Group 0
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_20
Pin Configuration n - Group 0
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_21
Pin Configuration n - Group 0
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_22
Pin Configuration n - Group 0
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_23
Pin Configuration n - Group 0
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_24
Pin Configuration n - Group 0
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_25
Pin Configuration n - Group 0
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_26
Pin Configuration n - Group 0
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_27
Pin Configuration n - Group 0
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_28
Pin Configuration n - Group 0
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_29
Pin Configuration n - Group 0
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_3
Pin Configuration n - Group 0
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_30
Pin Configuration n - Group 0
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_31
Pin Configuration n - Group 0
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_4
Pin Configuration n - Group 0
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_5
Pin Configuration n - Group 0
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_6
Pin Configuration n - Group 0
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_7
Pin Configuration n - Group 0
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_8
Pin Configuration n - Group 0
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_9
Pin Configuration n - Group 0
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG1
Pin Configuration n
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG10
Pin Configuration n
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG11
Pin Configuration n
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG12
Pin Configuration n
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG13
Pin Configuration n
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG14
Pin Configuration n
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG15
Pin Configuration n
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG16
Pin Configuration n
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG17
Pin Configuration n
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG18
Pin Configuration n
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG19
Pin Configuration n
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG2
Pin Configuration n
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG20
Pin Configuration n
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG21
Pin Configuration n
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG22
Pin Configuration n
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG23
Pin Configuration n
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG24
Pin Configuration n
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG25
Pin Configuration n
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG26
Pin Configuration n
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG27
Pin Configuration n
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG28
Pin Configuration n
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG29
Pin Configuration n
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG3
Pin Configuration n
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG30
Pin Configuration n
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG31
Pin Configuration n
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG4
Pin Configuration n
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG5
Pin Configuration n
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG6
Pin Configuration n
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG7
Pin Configuration n
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG8
Pin Configuration n
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG9
Pin Configuration n
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PMUX0
Peripheral Multiplexing n
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_0
Peripheral Multiplexing n - Group 0
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_1
Peripheral Multiplexing n - Group 0
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_10
Peripheral Multiplexing n - Group 0
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_11
Peripheral Multiplexing n - Group 0
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_12
Peripheral Multiplexing n - Group 0
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_13
Peripheral Multiplexing n - Group 0
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_14
Peripheral Multiplexing n - Group 0
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_15
Peripheral Multiplexing n - Group 0
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_2
Peripheral Multiplexing n - Group 0
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_3
Peripheral Multiplexing n - Group 0
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_4
Peripheral Multiplexing n - Group 0
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_5
Peripheral Multiplexing n - Group 0
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_6
Peripheral Multiplexing n - Group 0
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_7
Peripheral Multiplexing n - Group 0
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_8
Peripheral Multiplexing n - Group 0
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_9
Peripheral Multiplexing n - Group 0
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX1
Peripheral Multiplexing n
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX10
Peripheral Multiplexing n
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX11
Peripheral Multiplexing n
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX12
Peripheral Multiplexing n
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX13
Peripheral Multiplexing n
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX14
Peripheral Multiplexing n
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX15
Peripheral Multiplexing n
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX2
Peripheral Multiplexing n
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX3
Peripheral Multiplexing n
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX4
Peripheral Multiplexing n
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX5
Peripheral Multiplexing n
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX6
Peripheral Multiplexing n
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX7
Peripheral Multiplexing n
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX8
Peripheral Multiplexing n
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX9
Peripheral Multiplexing n
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
WRCONFIG
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
WRCONFIG1
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
PORT_IOBUS
Port Module
PORT
0x0
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
CTRL
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
CTRL1
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
write-only
DIR
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIR1
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIRCLR
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRCLR1
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRSET
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRSET1
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRTGL
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
DIRTGL1
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
IN
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
Port Data Input Value
0
32
IN1
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
Port Data Input Value
0
32
OUT
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
Port Data Output Value
0
32
OUT1
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
Port Data Output Value
0
32
OUTCLR
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
Port Data Output Value Clear
0
32
OUTCLR1
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
Port Data Output Value Clear
0
32
OUTSET
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
Port Data Output Value Set
0
32
OUTSET1
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
Port Data Output Value Set
0
32
OUTTGL
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
Port Data Output Value Toggle
0
32
OUTTGL1
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
Port Data Output Value Toggle
0
32
PINCFG0
Pin Configuration n
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_0
Pin Configuration n - Group 0
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_1
Pin Configuration n - Group 0
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_10
Pin Configuration n - Group 0
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_11
Pin Configuration n - Group 0
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_12
Pin Configuration n - Group 0
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_13
Pin Configuration n - Group 0
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_14
Pin Configuration n - Group 0
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_15
Pin Configuration n - Group 0
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_16
Pin Configuration n - Group 0
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_17
Pin Configuration n - Group 0
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_18
Pin Configuration n - Group 0
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_19
Pin Configuration n - Group 0
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_2
Pin Configuration n - Group 0
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_20
Pin Configuration n - Group 0
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_21
Pin Configuration n - Group 0
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_22
Pin Configuration n - Group 0
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_23
Pin Configuration n - Group 0
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_24
Pin Configuration n - Group 0
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_25
Pin Configuration n - Group 0
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_26
Pin Configuration n - Group 0
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_27
Pin Configuration n - Group 0
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_28
Pin Configuration n - Group 0
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_29
Pin Configuration n - Group 0
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_3
Pin Configuration n - Group 0
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_30
Pin Configuration n - Group 0
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_31
Pin Configuration n - Group 0
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_4
Pin Configuration n - Group 0
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_5
Pin Configuration n - Group 0
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_6
Pin Configuration n - Group 0
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_7
Pin Configuration n - Group 0
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_8
Pin Configuration n - Group 0
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG0_9
Pin Configuration n - Group 0
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
write-only
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG1
Pin Configuration n
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG10
Pin Configuration n
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG11
Pin Configuration n
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG12
Pin Configuration n
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG13
Pin Configuration n
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG14
Pin Configuration n
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG15
Pin Configuration n
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG16
Pin Configuration n
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG17
Pin Configuration n
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG18
Pin Configuration n
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG19
Pin Configuration n
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG2
Pin Configuration n
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG20
Pin Configuration n
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG21
Pin Configuration n
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG22
Pin Configuration n
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG23
Pin Configuration n
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG24
Pin Configuration n
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG25
Pin Configuration n
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG26
Pin Configuration n
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG27
Pin Configuration n
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG28
Pin Configuration n
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG29
Pin Configuration n
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG3
Pin Configuration n
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG30
Pin Configuration n
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG31
Pin Configuration n
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG4
Pin Configuration n
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG5
Pin Configuration n
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG6
Pin Configuration n
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG7
Pin Configuration n
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG8
Pin Configuration n
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG9
Pin Configuration n
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PMUX0
Peripheral Multiplexing n
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_0
Peripheral Multiplexing n - Group 0
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_1
Peripheral Multiplexing n - Group 0
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_10
Peripheral Multiplexing n - Group 0
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_11
Peripheral Multiplexing n - Group 0
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_12
Peripheral Multiplexing n - Group 0
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_13
Peripheral Multiplexing n - Group 0
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_14
Peripheral Multiplexing n - Group 0
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_15
Peripheral Multiplexing n - Group 0
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_2
Peripheral Multiplexing n - Group 0
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_3
Peripheral Multiplexing n - Group 0
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_4
Peripheral Multiplexing n - Group 0
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_5
Peripheral Multiplexing n - Group 0
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_6
Peripheral Multiplexing n - Group 0
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_7
Peripheral Multiplexing n - Group 0
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_8
Peripheral Multiplexing n - Group 0
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX0_9
Peripheral Multiplexing n - Group 0
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX1
Peripheral Multiplexing n
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX10
Peripheral Multiplexing n
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX11
Peripheral Multiplexing n
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX12
Peripheral Multiplexing n
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX13
Peripheral Multiplexing n
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX14
Peripheral Multiplexing n
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX15
Peripheral Multiplexing n
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX2
Peripheral Multiplexing n
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX3
Peripheral Multiplexing n
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX4
Peripheral Multiplexing n
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX5
Peripheral Multiplexing n
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX6
Peripheral Multiplexing n
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX7
Peripheral Multiplexing n
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX8
Peripheral Multiplexing n
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUX9
Peripheral Multiplexing n
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing Even
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
PMUXO
Peripheral Multiplexing Odd
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
WRCONFIG
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
WRCONFIG1
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
PTC
Peripheral Touch Controller
PTC
0x0
0x0
0x1
reserved
n
PTC
26
RTC
Real-Time Counter
RTC
0x0
0x0
0x1D
registers
n
0x0
0x1D
registers
n
0x0
0x1D
registers
n
0x0
0x1D
registers
n
RTC_INTREQ
3
RTC
3
ALARM
MODE2_ALARM Alarm n Value
0x18
32
read-write
n
0x0
0x0
DAY
Day
17
5
HOUR
Hour
12
5
HOURSelect
AM
Morning hour
0x00
PM
Afternoon hour
0x10
MINUTE
Minute
6
6
MONTH
Month
22
4
SECOND
Second
0
6
YEAR
Year
26
6
ALARM1
MODE2 Alarm n Value
0x18
32
read-write
n
0x0
0x0
DAY
Day
17
5
HOUR
Hour
12
5
HOURSelect
AM
Morning hour
0x0
PM
Afternoon hour
0x10
MINUTE
Minute
6
6
MONTH
Month
22
4
SECOND
Second
0
6
YEAR
Year
26
6
CLOCK
MODE2 Clock Value
0x10
32
read-write
n
0x0
0x0
DAY
Day
17
5
HOUR
Hour
12
5
HOURSelect
AM
AM when CLKREP in 12-hour
0x00
PM
PM when CLKREP in 12-hour
0x10
MINUTE
Minute
6
6
MONTH
Month
22
4
SECOND
Second
0
6
YEAR
Year
26
6
COMP
MODE0 Compare n Value
0x18
32
read-write
n
0x0
0x0
COMP
Compare Value
0
32
COMP0
MODE1 Compare n Value
0x18
16
read-write
n
0x0
0x0
COMP
Compare Value
0
16
COMP1
MODE1 Compare n Value
0x1A
16
read-write
n
0x0
0x0
COMP
Compare Value
0
16
COUNT
MODE1 Counter Value
0x10
16
read-write
n
0x0
0x0
COUNT
Counter Value
0
16
CTRL
MODE2 Control
0x0
16
read-write
n
0x0
0x0
CLKREP
Clock Representation
6
1
ENABLE
Enable
1
1
MATCHCLR
Clear on Match
7
1
MODE
Operating Mode
2
2
MODESelect
COUNT32
Mode 0: 32-bit Counter
0x0
COUNT16
Mode 1: 16-bit Counter
0x1
CLOCK
Mode 2: Clock/Calendar
0x2
PRESCALER
Prescaler
8
4
PRESCALERSelect
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x0
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x1
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x2
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x3
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x4
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x5
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x6
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x7
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x8
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0x9
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xA
SWRST
Software Reset
0
1
write-only
DBGCTRL
Debug Control
0xB
8
read-write
n
0x0
0x0
DBGRUN
Run During Debug
0
1
EVCTRL
MODE2 Event Control
0x4
16
read-write
n
0x0
0x0
ALARMEO0
Alarm 0 Event Output Enable
8
1
CMPEO0
Compare 0 Event Output Enable
8
1
CMPEO1
Compare 1 Event Output Enable
9
1
OVFEO
Overflow Event Output Enable
15
1
PEREO0
Periodic Interval 0 Event Output Enable
0
1
PEREO1
Periodic Interval 1 Event Output Enable
1
1
PEREO2
Periodic Interval 2 Event Output Enable
2
1
PEREO3
Periodic Interval 3 Event Output Enable
3
1
PEREO4
Periodic Interval 4 Event Output Enable
4
1
PEREO5
Periodic Interval 5 Event Output Enable
5
1
PEREO6
Periodic Interval 6 Event Output Enable
6
1
PEREO7
Periodic Interval 7 Event Output Enable
7
1
FREQCORR
Frequency Correction
0xC
8
read-write
n
0x0
0x0
SIGN
Correction Sign
7
1
VALUE
Correction Value
0
7
INTENCLR
MODE2 Interrupt Enable Clear
0x6
8
read-write
n
0x0
0x0
ALARM0
Alarm 0 Interrupt Enable
0
1
CMP0
Compare 0 Interrupt Enable
0
1
CMP1
Compare 1 Interrupt Enable
1
1
OVF
Overflow Interrupt Enable
7
1
SYNCRDY
Synchronization Ready Interrupt Enable
6
1
INTENSET
MODE2 Interrupt Enable Set
0x7
8
read-write
n
0x0
0x0
ALARM0
Alarm 0 Interrupt Enable
0
1
CMP0
Compare 0 Interrupt Enable
0
1
CMP1
Compare 1 Interrupt Enable
1
1
OVF
Overflow Interrupt Enable
7
1
SYNCRDY
Synchronization Ready Interrupt Enable
6
1
INTFLAG
MODE2 Interrupt Flag Status and Clear
0x8
8
read-write
n
0x0
0x0
ALARM0
Alarm 0
0
1
CMP0
Compare 0
0
1
CMP1
Compare 1
1
1
OVF
Overflow
7
1
SYNCRDY
Synchronization Ready
6
1
MASK
MODE2_ALARM Alarm n Mask
0x1C
8
read-write
n
0x0
0x0
SEL
Alarm Mask Selection
0
3
SELSelect
OFF
Alarm Disabled
0x0
SS
Match seconds only
0x1
MMSS
Match seconds and minutes only
0x2
HHMMSS
Match seconds, minutes, and hours only
0x3
DDHHMMSS
Match seconds, minutes, hours, and days only
0x4
MMDDHHMMSS
Match seconds, minutes, hours, days, and months only
0x5
YYMMDDHHMMSS
Match seconds, minutes, hours, days, months, and years
0x6
MASK1
MODE2 Alarm n Mask
0x1C
8
read-write
n
0x0
0x0
SEL
Alarm Mask Selection
0
3
SELSelect
OFF
Alarm Disabled
0x0
SS
Match seconds only
0x1
MMSS
Match seconds and minutes only
0x2
HHMMSS
Match seconds, minutes, and hours only
0x3
DDHHMMSS
Match seconds, minutes, hours, and days only
0x4
MMDDHHMMSS
Match seconds, minutes, hours, days, and months only
0x5
YYMMDDHHMMSS
Match seconds, minutes, hours, days, months, and years
0x6
PER
MODE1 Counter Period
0x14
16
read-write
n
0x0
0x0
PER
Counter Period
0
16
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
6
read-only
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
write-only
STATUS
Status
0xA
8
read-write
n
0x0
0x0
SYNCBUSY
Synchronization Busy
7
1
read-only
SBMATRIX
HSB Matrix
HMATRIXB
0x0
0x0
0x168
registers
n
PRAS
Priority A for Slave
0x0
32
read-write
n
0x0
0x0
PRBS
Priority B for Slave
0x4
32
read-write
n
0x0
0x0
SFR0
Special Function
0x110
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR1
Special Function
0x114
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR10
Special Function
0x138
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR11
Special Function
0x13C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR12
Special Function
0x140
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR13
Special Function
0x144
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR14
Special Function
0x148
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR15
Special Function
0x14C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR2
Special Function
0x118
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR3
Special Function
0x11C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR4
Special Function
0x120
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR5
Special Function
0x124
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR6
Special Function
0x128
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR7
Special Function
0x12C
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR8
Special Function
0x130
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SFR9
Special Function
0x134
32
read-write
n
0x0
0x0
SFR
Special Function Register
0
32
SERCOM0
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM0_INTREQ
9
SERCOM0
9
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SERCOM1
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM1_INTREQ
10
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SERCOM2
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM2_INTREQ
11
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SERCOM3
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM3_INTREQ
12
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SERCOM4
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM4_INTREQ
13
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SERCOM5
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
0x0
0x31
registers
n
SERCOM5_INTREQ
14
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
write-only
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
read-only
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
read-only
RXS
Receive Start Interrupt
3
1
write-only
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
read-only
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
read-only
DIR
Read/Write Direction
3
1
read-only
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
read-only
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
read-only
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
read-only
ENABLE
SERCOM Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
SYSOP
System Operation Synchronization Busy
2
1
read-only
SYSCTRL
System Control
SYSCTRL
0x0
0x0
0x51
registers
n
0x0
0x51
registers
n
0x0
0x51
registers
n
0x0
0x51
registers
n
SYSCTRL_INTREQ
1
SYSCTRL
1
BOD33
3.3V Brown-Out Detector (BOD33) Control
0x34
32
read-write
n
0x0
0x0
ACTION
BOD33 Action
3
2
ACTIONSelect
NONE
No action
0x0
RESET
The BOD33 generates a reset
0x1
INTERRUPT
The BOD33 generates an interrupt
0x2
CEN
Clock Enable
9
1
ENABLE
Enable
1
1
HYST
Hysteresis
2
1
LEVEL
BOD33 Threshold Level
16
6
MODE
Operation Mode
8
1
PSEL
Prescaler Select
12
4
PSELSelect
DIV2
Divide clock by 2
0x0
DIV4
Divide clock by 4
0x1
DIV8
Divide clock by 8
0x2
DIV16
Divide clock by 16
0x3
DIV32
Divide clock by 32
0x4
DIV64
Divide clock by 64
0x5
DIV128
Divide clock by 128
0x6
DIV256
Divide clock by 256
0x7
DIV512
Divide clock by 512
0x8
DIV1K
Divide clock by 1024
0x9
DIV2K
Divide clock by 2048
0xA
DIV4K
Divide clock by 4096
0xB
DIV8K
Divide clock by 8192
0xC
DIV16K
Divide clock by 16384
0xD
DIV32K
Divide clock by 32768
0xE
DIV64K
Divide clock by 65536
0xF
RUNSTDBY
Run in Standby
6
1
DFLLCTRL
DFLL48M Control
0x24
16
read-write
n
0x0
0x0
BPLCKC
Bypass Coarse Lock
10
1
CCDIS
Chill Cycle Disable
8
1
ENABLE
DFLL Enable
1
1
LLAW
Lose Lock After Wake
4
1
MODE
Operating Mode Selection
2
1
ONDEMAND
On Demand Control
7
1
QLDIS
Quick Lock Disable
9
1
RUNSTDBY
Run in Standby
6
1
STABLE
Stable DFLL Frequency
3
1
USBCRM
USB Clock Recovery Mode
5
1
WAITLOCK
Wait Lock
11
1
DFLLMUL
DFLL48M Multiplier
0x2C
32
read-write
n
0x0
0x0
CSTEP
Coarse Maximum Step
26
6
FSTEP
Fine Maximum Step
16
10
MUL
DFLL Multiply Factor
0
16
DFLLSYNC
DFLL48M Synchronization
0x30
8
read-write
n
0x0
0x0
READREQ
Read Request
7
1
write-only
DFLLVAL
DFLL48M Value
0x28
32
read-write
n
0x0
0x0
COARSE
Coarse Value
10
6
DIFF
Multiplication Ratio Difference
16
16
read-only
FINE
Fine Value
0
10
DPLLCTRLA
DPLL Control A
0x44
8
read-write
n
0x0
0x0
ENABLE
DPLL Enable
1
1
ONDEMAND
On Demand Clock Activation
7
1
RUNSTDBY
Run in Standby
6
1
DPLLCTRLB
DPLL Control B
0x4C
32
read-write
n
0x0
0x0
DIV
Clock Divider
16
11
FILTER
Proportional Integral Filter Selection
0
2
FILTERSelect
DEFAULT
Default filter mode
0x0
LBFILT
Low bandwidth filter
0x1
HBFILT
High bandwidth filter
0x2
HDFILT
High damping filter
0x3
LBYPASS
Lock Bypass
12
1
LPEN
Low-Power Enable
2
1
LTIME
Lock Time
8
3
LTIMESelect
DEFAULT
No time-out
0x0
8MS
Time-out if no lock within 8 ms
0x4
9MS
Time-out if no lock within 9 ms
0x5
10MS
Time-out if no lock within 10 ms
0x6
11MS
Time-out if no lock within 11 ms
0x7
REFCLK
Reference Clock Selection
4
2
REFCLKSelect
REF0
CLK_DPLL_REF0 clock reference
0x0
REF1
CLK_DPLL_REF1 clock reference
0x1
GCLK
GCLK_DPLL clock reference
0x2
WUF
Wake Up Fast
3
1
DPLLRATIO
DPLL Ratio Control
0x48
32
read-write
n
0x0
0x0
LDR
Loop Divider Ratio
0
12
LDRFRAC
Loop Divider Ratio Fractional Part
16
4
DPLLSTATUS
DPLL Status
0x50
8
read-only
n
0x0
0x0
CLKRDY
Output Clock Ready
1
1
read-only
DIV
Divider Enable
3
1
read-only
ENABLE
DPLL Enable
2
1
read-only
LOCK
DPLL Lock Status
0
1
read-only
INTENCLR
Interrupt Enable Clear
0x0
32
read-write
n
0x0
0x0
B33SRDY
BOD33 Synchronization Ready Interrupt Enable
11
1
BOD33DET
BOD33 Detection Interrupt Enable
10
1
BOD33RDY
BOD33 Ready Interrupt Enable
9
1
DFLLLCKC
DFLL Lock Coarse Interrupt Enable
7
1
DFLLLCKF
DFLL Lock Fine Interrupt Enable
6
1
DFLLOOB
DFLL Out Of Bounds Interrupt Enable
5
1
DFLLRCS
DFLL Reference Clock Stopped Interrupt Enable
8
1
DFLLRDY
DFLL Ready Interrupt Enable
4
1
DPLLLCKF
DPLL Lock Fall Interrupt Enable
16
1
DPLLLCKR
DPLL Lock Rise Interrupt Enable
15
1
DPLLLTO
DPLL Lock Timeout Interrupt Enable
17
1
OSC32KRDY
OSC32K Ready Interrupt Enable
2
1
OSC8MRDY
OSC8M Ready Interrupt Enable
3
1
XOSC32KRDY
XOSC32K Ready Interrupt Enable
1
1
XOSCRDY
XOSC Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x4
32
read-write
n
0x0
0x0
B33SRDY
BOD33 Synchronization Ready Interrupt Enable
11
1
BOD33DET
BOD33 Detection Interrupt Enable
10
1
BOD33RDY
BOD33 Ready Interrupt Enable
9
1
DFLLLCKC
DFLL Lock Coarse Interrupt Enable
7
1
DFLLLCKF
DFLL Lock Fine Interrupt Enable
6
1
DFLLOOB
DFLL Out Of Bounds Interrupt Enable
5
1
DFLLRCS
DFLL Reference Clock Stopped Interrupt Enable
8
1
DFLLRDY
DFLL Ready Interrupt Enable
4
1
DPLLLCKF
DPLL Lock Fall Interrupt Enable
16
1
DPLLLCKR
DPLL Lock Rise Interrupt Enable
15
1
DPLLLTO
DPLL Lock Timeout Interrupt Enable
17
1
OSC32KRDY
OSC32K Ready Interrupt Enable
2
1
OSC8MRDY
OSC8M Ready Interrupt Enable
3
1
XOSC32KRDY
XOSC32K Ready Interrupt Enable
1
1
XOSCRDY
XOSC Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x8
32
read-write
n
0x0
0x0
B33SRDY
BOD33 Synchronization Ready
11
1
BOD33DET
BOD33 Detection
10
1
BOD33RDY
BOD33 Ready
9
1
DFLLLCKC
DFLL Lock Coarse
7
1
DFLLLCKF
DFLL Lock Fine
6
1
DFLLOOB
DFLL Out Of Bounds
5
1
DFLLRCS
DFLL Reference Clock Stopped
8
1
DFLLRDY
DFLL Ready
4
1
DPLLLCKF
DPLL Lock Fall
16
1
DPLLLCKR
DPLL Lock Rise
15
1
DPLLLTO
DPLL Lock Timeout
17
1
OSC32KRDY
OSC32K Ready
2
1
OSC8MRDY
OSC8M Ready
3
1
XOSC32KRDY
XOSC32K Ready
1
1
XOSCRDY
XOSC Ready
0
1
OSC32K
32kHz Internal Oscillator (OSC32K) Control
0x18
32
read-write
n
0x0
0x0
CALIB
Oscillator Calibration
16
7
EN1K
1kHz Output Enable
3
1
EN32K
32kHz Output Enable
2
1
ENABLE
Oscillator Enable
1
1
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STARTUP
Oscillator Start-Up Time
8
3
STARTUPSelect
CYCLE3
0.092 ms
0
CYCLE4
0.122 ms
1
CYCLE6
0.183 ms
2
CYCLE10
0.305 ms
3
CYCLE18
0.549 ms
4
CYCLE34
1.038 ms
5
CYCLE66
2.014 ms
6
CYCLE130
3.967 ms
7
WRTLOCK
Write Lock
12
1
OSC8M
8MHz Internal Oscillator (OSC8M) Control
0x20
32
read-write
n
0x0
0x0
CALIB
Oscillator Calibration
16
12
ENABLE
Oscillator Enable
1
1
FRANGE
Oscillator Frequency Range
30
2
FRANGESelect
0
4 to 6MHz
0x0
1
6 to 8MHz
0x1
2
8 to 11MHz
0x2
3
11 to 15MHz
0x3
ONDEMAND
On Demand Control
7
1
PRESC
Oscillator Prescaler
8
2
PRESCSelect
0
1
0x0
1
2
0x1
2
4
0x2
3
8
0x3
RUNSTDBY
Run in Standby
6
1
OSCULP32K
32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
0x1C
8
read-write
n
0x0
0x0
CALIB
Oscillator Calibration
0
5
WRTLOCK
Write Lock
7
1
PCLKSR
Power and Clocks Status
0xC
32
read-only
n
0x0
0x0
B33SRDY
BOD33 Synchronization Ready
11
1
read-only
BOD33DET
BOD33 Detection
10
1
read-only
BOD33RDY
BOD33 Ready
9
1
read-only
DFLLLCKC
DFLL Lock Coarse
7
1
read-only
DFLLLCKF
DFLL Lock Fine
6
1
read-only
DFLLOOB
DFLL Out Of Bounds
5
1
read-only
DFLLRCS
DFLL Reference Clock Stopped
8
1
read-only
DFLLRDY
DFLL Ready
4
1
read-only
DPLLLCKF
DPLL Lock Fall
16
1
read-only
DPLLLCKR
DPLL Lock Rise
15
1
read-only
DPLLLTO
DPLL Lock Timeout
17
1
read-only
OSC32KRDY
OSC32K Ready
2
1
read-only
OSC8MRDY
OSC8M Ready
3
1
read-only
XOSC32KRDY
XOSC32K Ready
1
1
read-only
XOSCRDY
XOSC Ready
0
1
read-only
VREF
Voltage References System (VREF) Control
0x40
32
read-write
n
0x0
0x0
BGOUTEN
Bandgap Output Enable
2
1
CALIB
Bandgap Voltage Generator Calibration
16
11
TSEN
Temperature Sensor Enable
1
1
VREG
Voltage Regulator System (VREG) Control
0x3C
16
read-write
n
0x0
0x0
FORCELDO
Force LDO Voltage Regulator
13
1
RUNSTDBY
Run in Standby
6
1
XOSC
External Multipurpose Crystal Oscillator (XOSC) Control
0x10
16
read-write
n
0x0
0x0
AMPGC
Automatic Amplitude Gain Control
11
1
ENABLE
Oscillator Enable
1
1
GAIN
Oscillator Gain
8
3
GAINSelect
0
2MHz
0x0
1
4MHz
0x1
2
8MHz
0x2
3
16MHz
0x3
4
30MHz
0x4
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STARTUP
Start-Up Time
12
4
STARTUPSelect
CYCLE1
31 us
0
CYCLE2
61 us
1
CYCLE1024
31250 us
10
CYCLE2048
62500 us
11
CYCLE4096
125000 us
12
CYCLE8192
250000 us
13
CYCLE16384
500000 us
14
CYCLE32768
1000000 us
15
CYCLE4
122 us
2
CYCLE8
244 us
3
CYCLE16
488 us
4
CYCLE32
977 us
5
CYCLE64
1953 us
6
CYCLE128
3906 us
7
CYCLE256
7813 us
8
CYCLE512
15625 us
9
XTALEN
Crystal Oscillator Enable
2
1
XOSC32K
32kHz External Crystal Oscillator (XOSC32K) Control
0x14
16
read-write
n
0x0
0x0
AAMPEN
Automatic Amplitude Control Enable
5
1
EN1K
1kHz Output Enable
4
1
EN32K
32kHz Output Enable
3
1
ENABLE
Oscillator Enable
1
1
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STARTUP
Oscillator Start-Up Time
8
3
STARTUPSelect
CYCLE1
0.122 ms
0
CYCLE32
1.068 ms
1
CYCLE2048
62.592 ms
2
CYCLE4096
125.092 ms
3
CYCLE16384
500.092 ms
4
CYCLE32768
1000.092 ms
5
CYCLE65536
2000.092 ms
6
CYCLE131072
4000.092 ms
7
WRTLOCK
Write Lock
12
1
XTALEN
Crystal Oscillator Enable
2
1
SystemControl
System Control Registers
SystemControl
0x0
0x0
0xD34
registers
n
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness, 0=little, 1=big
15
1
ENDIANNESSSelect
VALUE_0
Little-endian
0
VALUE_1
Big-endian
1
SYSRESETREQ
System Reset Request
2
1
SYSRESETREQSelect
VALUE_0
No system reset request
0
VALUE_1
Asserts a signal to the outer system that requests a reset
1
VECTCLRACTIVE
Debug: Clear state information
1
1
VECTKEY
Register key (0x05FA)
16
16
CCR
Configuration and Control Register
0xD14
32
read-only
n
0x0
0x0
STKALIGN
Stack 8-byte aligned on exception entry
9
1
STKALIGNSelect
VALUE_0
4-byte aligned
0
VALUE_1
8-byte aligned
1
UNALIGN_TRP
Unaligned accesses generates a Hard Fault
3
1
UNALIGN_TRPSelect
VALUE_0
Do not trap unaligned halfword and word accesses
0
VALUE_1
Trap unaligned halfword and word accesses
1
CPUID
CPUID Base Register
0xD00
32
read-only
n
0x0
0x0
ARCHITECTURE
Processor Architecture, 0xC=ARMv6-M
16
4
IMPLEMENTER
Implementer code, ARM=0x41
24
8
PARTNO
Processor Part Number, 0xC60=Cortex-M0+
4
12
REVISION
Minor revision number
0
4
VARIANT
Major revision number
20
4
DFSR
Debug Fault Status Register
0xD30
32
read-write
n
0x0
0x0
BKPT
Breakpoint debug event
1
1
DWTTRAP
DWT debug event
2
1
EXTERNAL
EDBGRQ debug event
4
1
HALTED
Halt request debug event active
0
1
VCATCH
Vector catch debug event
3
1
ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
ISRPENDING
Debug: NVIC interrupt pending
22
1
ISRPREEMPT
Debug: Pending exception serviced on exit from debug halt
23
1
NMIPENDSET
NMI set-pending bit
31
1
NMIPENDSETSelect
VALUE_0
Write: no effect read: NMI exception is not pending
0
VALUE_1
Write: changes NMI exception state to pending read: NMI exception is pending
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the SysTick exception
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSTSETSelect
VALUE_0
Write: no effect read: SysTick exception is not pending
0
VALUE_1
Write: changes SysTick exception state to pending read: SysTick exception is pending
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the PendSV exception
1
PENDSVSET
PendSV set-pending bit
28
1
PENDSVSETSelect
VALUE_0
Write: no effect read: PendSV exception is not pending
0
VALUE_1
Write: changes PendSV exception state to pending read: PendSV exception is pending
1
VECTACTIVE
Debug: Exception number of currently executing exception, or 0 if thread mode
0
9
VECTPENDING
Exception number of the highest priority pending enabled exception
12
9
SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit
4
1
SEVONPENDSelect
VALUE_0
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0
VALUE_1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
1
SLEEPDEEP
Uses Deep Sleep as low power mode
2
1
SLEEPDEEPSelect
VALUE_0
Sleep
0
VALUE_1
Deep sleep
1
SLEEPONEXIT
Sleep-On-Exit when exiting Handler mode
1
1
SLEEPONEXITSelect
VALUE_0
O not sleep when returning to Thread mode
0
VALUE_1
Enter sleep, or deep sleep, on return from an ISR
1
SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
15
1
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
24
8
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14, PendSV
16
8
PRI_15
Priority of system handler 15, SysTick exception
24
8
VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
SysTick
System timer
SysTick
0x0
0x0
0x10
registers
n
CALIB
SysTick Calibration Value Register
0xC
32
read-only
n
0x0
0x0
NOREF
No Separate Reference Clock
31
1
NOREFSelect
VALUE_0
The reference clock is provided
0
VALUE_1
The reference clock is not provided
1
SKEW
TENMS is rounded from non-integer ratio
30
1
SKEWSelect
VALUE_0
10ms calibration value is exact
0
VALUE_1
10ms calibration value is inexact, because of the clock frequency
1
TENMS
Reload value to use for 10ms timing
0
24
CSR
SysTick Control and Status Register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock Source 0=external, 1=processor
2
1
CLKSOURCESelect
VALUE_0
External clock
0
VALUE_1
Processor clock
1
COUNTFLAG
Timer counted to 0 since last read of register
16
1
ENABLE
SysTick Counter Enable
0
1
ENABLESelect
VALUE_0
Counter disabled
0
VALUE_1
Counter enabled
1
TICKINT
SysTick Exception Request Enable
1
1
TICKINTSelect
VALUE_0
Counting down to 0 does not assert the SysTick exception request
0
VALUE_1
Counting down to 0 asserts the SysTick exception request
1
CVR
SysTick Current Value Register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current value at the time the register is accessed
0
24
RVR
SysTick Reload Value Register
0x4
32
read-write
n
0x0
0x0
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
TC3
Basic Timer Counter
TC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
TC3_INTREQ
18
TC3
18
CC0
COUNT32 Compare/Capture
0x18
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
CC1
COUNT32 Compare/Capture
0x1C
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
COUNT
COUNT32 Counter Value
0x10
32
read-write
n
0x0
0x0
COUNT
Count Value
0
32
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
TC Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0x0
DIV2
Prescaler: GCLK_TC/2
0x1
DIV4
Prescaler: GCLK_TC/4
0x2
DIV8
Prescaler: GCLK_TC/8
0x3
DIV16
Prescaler: GCLK_TC/16
0x4
DIV64
Prescaler: GCLK_TC/64
0x5
DIV256
Prescaler: GCLK_TC/256
0x6
DIV1024
Prescaler: GCLK_TC/1024
0x7
PRESCSYNC
Prescaler and Counter Synchronization
12
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
2
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
write-only
WAVEGEN
Waveform Generation Operation
5
2
WAVEGENSelect
NFRQ
0
MFRQ
1
NPWM
2
MPWM
3
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0x0
RETRIGGER
Force a start, restart or retrigger
0x1
STOP
Force a stop
0x2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLC
Control C
0x6
8
read-write
n
0x0
0x0
CPTEN0
Capture Channel 0 Enable
4
1
CPTEN1
Capture Channel 1 Enable
5
1
INVEN0
Output Waveform 0 Invert Enable
0
1
INVEN1
Output Waveform 1 Invert Enable
1
1
DBGCTRL
Debug Control
0x8
8
read-write
n
0x0
0x0
DBGRUN
Debug Run Mode
0
1
EVCTRL
Event Control
0xA
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
PPW
Period captured in CC0, pulse width in CC1
5
PWP
Period captured in CC1, pulse width in CC0
6
MCEO0
Match or Capture Channel 0 Event Output Enable
12
1
MCEO1
Match or Capture Channel 1 Event Output Enable
13
1
OVFEO
Overflow/Underflow Event Output Enable
8
1
TCEI
TC Event Input
5
1
TCINV
TC Inverted Event Input
4
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTENSET
Interrupt Enable Set
0xD
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTFLAG
Interrupt Flag Status and Clear
0xE
8
read-write
n
0x0
0x0
ERR
Error
1
1
MC0
Match or Capture Channel 0
4
1
MC1
Match or Capture Channel 1
5
1
OVF
Overflow
0
1
SYNCRDY
Synchronization Ready
3
1
PER
COUNT8 Period Value
0x14
8
read-write
n
0x0
0x0
PER
Period Value
0
8
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
5
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
STATUS
Status
0xF
8
read-only
n
0x0
0x0
SLAVE
Slave
4
1
read-only
STOP
Stop
3
1
read-only
SYNCBUSY
Synchronization Busy
7
1
read-only
TC4
Basic Timer Counter
TC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
TC4_INTREQ
19
CC0
COUNT32 Compare/Capture
0x18
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
CC1
COUNT32 Compare/Capture
0x1C
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
COUNT
COUNT32 Counter Value
0x10
32
read-write
n
0x0
0x0
COUNT
Count Value
0
32
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
TC Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0x0
DIV2
Prescaler: GCLK_TC/2
0x1
DIV4
Prescaler: GCLK_TC/4
0x2
DIV8
Prescaler: GCLK_TC/8
0x3
DIV16
Prescaler: GCLK_TC/16
0x4
DIV64
Prescaler: GCLK_TC/64
0x5
DIV256
Prescaler: GCLK_TC/256
0x6
DIV1024
Prescaler: GCLK_TC/1024
0x7
PRESCSYNC
Prescaler and Counter Synchronization
12
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
2
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
write-only
WAVEGEN
Waveform Generation Operation
5
2
WAVEGENSelect
NFRQ
0
MFRQ
1
NPWM
2
MPWM
3
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0x0
RETRIGGER
Force a start, restart or retrigger
0x1
STOP
Force a stop
0x2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLC
Control C
0x6
8
read-write
n
0x0
0x0
CPTEN0
Capture Channel 0 Enable
4
1
CPTEN1
Capture Channel 1 Enable
5
1
INVEN0
Output Waveform 0 Invert Enable
0
1
INVEN1
Output Waveform 1 Invert Enable
1
1
DBGCTRL
Debug Control
0x8
8
read-write
n
0x0
0x0
DBGRUN
Debug Run Mode
0
1
EVCTRL
Event Control
0xA
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
PPW
Period captured in CC0, pulse width in CC1
5
PWP
Period captured in CC1, pulse width in CC0
6
MCEO0
Match or Capture Channel 0 Event Output Enable
12
1
MCEO1
Match or Capture Channel 1 Event Output Enable
13
1
OVFEO
Overflow/Underflow Event Output Enable
8
1
TCEI
TC Event Input
5
1
TCINV
TC Inverted Event Input
4
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTENSET
Interrupt Enable Set
0xD
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTFLAG
Interrupt Flag Status and Clear
0xE
8
read-write
n
0x0
0x0
ERR
Error
1
1
MC0
Match or Capture Channel 0
4
1
MC1
Match or Capture Channel 1
5
1
OVF
Overflow
0
1
SYNCRDY
Synchronization Ready
3
1
PER
COUNT8 Period Value
0x14
8
read-write
n
0x0
0x0
PER
Period Value
0
8
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
5
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
STATUS
Status
0xF
8
read-only
n
0x0
0x0
SLAVE
Slave
4
1
read-only
STOP
Stop
3
1
read-only
SYNCBUSY
Synchronization Busy
7
1
read-only
TC5
Basic Timer Counter
TC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
TC5_INTREQ
20
CC0
COUNT32 Compare/Capture
0x18
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
CC1
COUNT32 Compare/Capture
0x1C
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
COUNT
COUNT32 Counter Value
0x10
32
read-write
n
0x0
0x0
COUNT
Count Value
0
32
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
TC Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0x0
DIV2
Prescaler: GCLK_TC/2
0x1
DIV4
Prescaler: GCLK_TC/4
0x2
DIV8
Prescaler: GCLK_TC/8
0x3
DIV16
Prescaler: GCLK_TC/16
0x4
DIV64
Prescaler: GCLK_TC/64
0x5
DIV256
Prescaler: GCLK_TC/256
0x6
DIV1024
Prescaler: GCLK_TC/1024
0x7
PRESCSYNC
Prescaler and Counter Synchronization
12
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
2
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
write-only
WAVEGEN
Waveform Generation Operation
5
2
WAVEGENSelect
NFRQ
0
MFRQ
1
NPWM
2
MPWM
3
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0x0
RETRIGGER
Force a start, restart or retrigger
0x1
STOP
Force a stop
0x2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLC
Control C
0x6
8
read-write
n
0x0
0x0
CPTEN0
Capture Channel 0 Enable
4
1
CPTEN1
Capture Channel 1 Enable
5
1
INVEN0
Output Waveform 0 Invert Enable
0
1
INVEN1
Output Waveform 1 Invert Enable
1
1
DBGCTRL
Debug Control
0x8
8
read-write
n
0x0
0x0
DBGRUN
Debug Run Mode
0
1
EVCTRL
Event Control
0xA
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
PPW
Period captured in CC0, pulse width in CC1
5
PWP
Period captured in CC1, pulse width in CC0
6
MCEO0
Match or Capture Channel 0 Event Output Enable
12
1
MCEO1
Match or Capture Channel 1 Event Output Enable
13
1
OVFEO
Overflow/Underflow Event Output Enable
8
1
TCEI
TC Event Input
5
1
TCINV
TC Inverted Event Input
4
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTENSET
Interrupt Enable Set
0xD
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTFLAG
Interrupt Flag Status and Clear
0xE
8
read-write
n
0x0
0x0
ERR
Error
1
1
MC0
Match or Capture Channel 0
4
1
MC1
Match or Capture Channel 1
5
1
OVF
Overflow
0
1
SYNCRDY
Synchronization Ready
3
1
PER
COUNT8 Period Value
0x14
8
read-write
n
0x0
0x0
PER
Period Value
0
8
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
5
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
STATUS
Status
0xF
8
read-only
n
0x0
0x0
SLAVE
Slave
4
1
read-only
STOP
Stop
3
1
read-only
SYNCBUSY
Synchronization Busy
7
1
read-only
TC6
Basic Timer Counter
TC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
TC6_INTREQ
21
CC0
COUNT32 Compare/Capture
0x18
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
CC1
COUNT32 Compare/Capture
0x1C
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
COUNT
COUNT32 Counter Value
0x10
32
read-write
n
0x0
0x0
COUNT
Count Value
0
32
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
TC Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0x0
DIV2
Prescaler: GCLK_TC/2
0x1
DIV4
Prescaler: GCLK_TC/4
0x2
DIV8
Prescaler: GCLK_TC/8
0x3
DIV16
Prescaler: GCLK_TC/16
0x4
DIV64
Prescaler: GCLK_TC/64
0x5
DIV256
Prescaler: GCLK_TC/256
0x6
DIV1024
Prescaler: GCLK_TC/1024
0x7
PRESCSYNC
Prescaler and Counter Synchronization
12
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
2
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
write-only
WAVEGEN
Waveform Generation Operation
5
2
WAVEGENSelect
NFRQ
0
MFRQ
1
NPWM
2
MPWM
3
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0x0
RETRIGGER
Force a start, restart or retrigger
0x1
STOP
Force a stop
0x2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLC
Control C
0x6
8
read-write
n
0x0
0x0
CPTEN0
Capture Channel 0 Enable
4
1
CPTEN1
Capture Channel 1 Enable
5
1
INVEN0
Output Waveform 0 Invert Enable
0
1
INVEN1
Output Waveform 1 Invert Enable
1
1
DBGCTRL
Debug Control
0x8
8
read-write
n
0x0
0x0
DBGRUN
Debug Run Mode
0
1
EVCTRL
Event Control
0xA
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
PPW
Period captured in CC0, pulse width in CC1
5
PWP
Period captured in CC1, pulse width in CC0
6
MCEO0
Match or Capture Channel 0 Event Output Enable
12
1
MCEO1
Match or Capture Channel 1 Event Output Enable
13
1
OVFEO
Overflow/Underflow Event Output Enable
8
1
TCEI
TC Event Input
5
1
TCINV
TC Inverted Event Input
4
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTENSET
Interrupt Enable Set
0xD
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTFLAG
Interrupt Flag Status and Clear
0xE
8
read-write
n
0x0
0x0
ERR
Error
1
1
MC0
Match or Capture Channel 0
4
1
MC1
Match or Capture Channel 1
5
1
OVF
Overflow
0
1
SYNCRDY
Synchronization Ready
3
1
PER
COUNT8 Period Value
0x14
8
read-write
n
0x0
0x0
PER
Period Value
0
8
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
5
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
STATUS
Status
0xF
8
read-only
n
0x0
0x0
SLAVE
Slave
4
1
read-only
STOP
Stop
3
1
read-only
SYNCBUSY
Synchronization Busy
7
1
read-only
TC7
Basic Timer Counter
TC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
0x0
0x20
registers
n
TC7_INTREQ
22
CC0
COUNT32 Compare/Capture
0x18
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
CC1
COUNT32 Compare/Capture
0x1C
32
read-write
n
0x0
0x0
CC
Compare/Capture Value
0
32
COUNT
COUNT32 Counter Value
0x10
32
read-write
n
0x0
0x0
COUNT
Count Value
0
32
CTRLA
Control A
0x0
16
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
TC Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0x0
DIV2
Prescaler: GCLK_TC/2
0x1
DIV4
Prescaler: GCLK_TC/4
0x2
DIV8
Prescaler: GCLK_TC/8
0x3
DIV16
Prescaler: GCLK_TC/16
0x4
DIV64
Prescaler: GCLK_TC/64
0x5
DIV256
Prescaler: GCLK_TC/256
0x6
DIV1024
Prescaler: GCLK_TC/1024
0x7
PRESCSYNC
Prescaler and Counter Synchronization
12
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
2
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
write-only
WAVEGEN
Waveform Generation Operation
5
2
WAVEGENSelect
NFRQ
0
MFRQ
1
NPWM
2
MPWM
3
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
6
2
CMDSelect
NONE
No action
0x0
RETRIGGER
Force a start, restart or retrigger
0x1
STOP
Force a stop
0x2
DIR
Counter Direction
0
1
ONESHOT
One-Shot
2
1
CTRLC
Control C
0x6
8
read-write
n
0x0
0x0
CPTEN0
Capture Channel 0 Enable
4
1
CPTEN1
Capture Channel 1 Enable
5
1
INVEN0
Output Waveform 0 Invert Enable
0
1
INVEN1
Output Waveform 1 Invert Enable
1
1
DBGCTRL
Debug Control
0x8
8
read-write
n
0x0
0x0
DBGRUN
Debug Run Mode
0
1
EVCTRL
Event Control
0xA
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
PPW
Period captured in CC0, pulse width in CC1
5
PWP
Period captured in CC1, pulse width in CC0
6
MCEO0
Match or Capture Channel 0 Event Output Enable
12
1
MCEO1
Match or Capture Channel 1 Event Output Enable
13
1
OVFEO
Overflow/Underflow Event Output Enable
8
1
TCEI
TC Event Input
5
1
TCINV
TC Inverted Event Input
4
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTENSET
Interrupt Enable Set
0xD
8
read-write
n
0x0
0x0
ERR
Error Interrupt Enable
1
1
MC0
Match or Capture Channel 0 Interrupt Enable
4
1
MC1
Match or Capture Channel 1 Interrupt Enable
5
1
OVF
Overflow Interrupt Enable
0
1
SYNCRDY
Synchronization Ready Interrupt Enable
3
1
INTFLAG
Interrupt Flag Status and Clear
0xE
8
read-write
n
0x0
0x0
ERR
Error
1
1
MC0
Match or Capture Channel 0
4
1
MC1
Match or Capture Channel 1
5
1
OVF
Overflow
0
1
SYNCRDY
Synchronization Ready
3
1
PER
COUNT8 Period Value
0x14
8
read-write
n
0x0
0x0
PER
Period Value
0
8
READREQ
Read Request
0x2
16
read-write
n
0x0
0x0
ADDR
Address
0
5
RCONT
Read Continuously
14
1
RREQ
Read Request
15
1
STATUS
Status
0xF
8
read-only
n
0x0
0x0
SLAVE
Slave
4
1
read-only
STOP
Stop
3
1
read-only
SYNCBUSY
Synchronization Busy
7
1
read-only
TCC0
Timer Counter Control
TCC
0x0
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
TCC0_INTREQ
15
TCC0
15
CC0
Compare and Capture
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC0_DITH4
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC0_DITH5
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC0_DITH6
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC1
Compare and Capture
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC1_DITH4
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC1_DITH5
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC1_DITH6
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC2
Compare and Capture
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC2_DITH4
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC2_DITH5
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC2_DITH6
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC3
Compare and Capture
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC3_DITH4
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC3_DITH5
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC3_DITH6
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CCB0
Compare and Capture Buffer
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB0_DITH4
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB0_DITH5
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB0_DITH6
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB1
Compare and Capture Buffer
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB1_DITH4
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB1_DITH5
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB1_DITH6
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB2
Compare and Capture Buffer
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB2_DITH4
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB2_DITH5
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB2_DITH6
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB3
Compare and Capture Buffer
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB3_DITH4
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB3_DITH5
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB3_DITH6
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH4_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH5_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH6_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CC_DITH4_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH5_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH6_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
COUNT
Count
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
24
COUNT_DITH4
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH4_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH5
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH5_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH6
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
COUNT_DITH6_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
14
1
CPTEN0
Capture Channel 0 Enable
24
1
CPTEN1
Capture Channel 1 Enable
25
1
CPTEN2
Capture Channel 2 Enable
26
1
CPTEN3
Capture Channel 3 Enable
27
1
ENABLE
Enable
1
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
No division
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV64
Divide by 64
5
DIV256
Divide by 256
6
DIV1024
Divide by 1024
7
PRESCSYNC
Prescaler and Counter Synchronization Selection
12
2
PRESCSYNCSelect
GCLK
Reload or reset counter on next GCLK
0
PRESC
Reload or reset counter on next prescaler clock
1
RESYNC
Reload or reset counter on next GCLK and reset prescaler counter
2
RESOLUTION
Enhanced Resolution
5
2
RESOLUTIONSelect
NONE
Dithering is disabled
0
DITH4
Dithering is done every 16 PWM frames
1
DITH5
Dithering is done every 32 PWM frames
2
DITH6
Dithering is done every 64 PWM frames
3
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
DBGCTRL
Debug Control
0x1E
8
read-write
n
0x0
0x0
DBGRUN
Debug Running Mode
0
1
FDDBD
Fault Detection on Debug Break Detection
2
1
DRVCTRL
Driver Control
0x18
32
read-write
n
0x0
0x0
FILTERVAL0
Non-Recoverable Fault Input 0 Filter Value
24
4
FILTERVAL1
Non-Recoverable Fault Input 1 Filter Value
28
4
INVEN0
Output Waveform 0 Inversion
16
1
INVEN1
Output Waveform 1 Inversion
17
1
INVEN2
Output Waveform 2 Inversion
18
1
INVEN3
Output Waveform 3 Inversion
19
1
INVEN4
Output Waveform 4 Inversion
20
1
INVEN5
Output Waveform 5 Inversion
21
1
INVEN6
Output Waveform 6 Inversion
22
1
INVEN7
Output Waveform 7 Inversion
23
1
NRE0
Non-Recoverable State 0 Output Enable
0
1
NRE1
Non-Recoverable State 1 Output Enable
1
1
NRE2
Non-Recoverable State 2 Output Enable
2
1
NRE3
Non-Recoverable State 3 Output Enable
3
1
NRE4
Non-Recoverable State 4 Output Enable
4
1
NRE5
Non-Recoverable State 5 Output Enable
5
1
NRE6
Non-Recoverable State 6 Output Enable
6
1
NRE7
Non-Recoverable State 7 Output Enable
7
1
NRV0
Non-Recoverable State 0 Output Value
8
1
NRV1
Non-Recoverable State 1 Output Value
9
1
NRV2
Non-Recoverable State 2 Output Value
10
1
NRV3
Non-Recoverable State 3 Output Value
11
1
NRV4
Non-Recoverable State 4 Output Value
12
1
NRV5
Non-Recoverable State 5 Output Value
13
1
NRV6
Non-Recoverable State 6 Output Value
14
1
NRV7
Non-Recoverable State 7 Output Value
15
1
EVCTRL
Event Control
0x20
32
read-write
n
0x0
0x0
CNTEO
Timer/counter Output Event Enable
10
1
CNTSEL
Timer/counter Output Event Mode
6
2
CNTSELSelect
START
An interrupt/event is generated when a new counter cycle starts
0
END
An interrupt/event is generated when a counter cycle ends
1
BETWEEN
An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
2
BOUNDARY
An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
3
EVACT0
Timer/counter Input Event0 Action
0
3
EVACT0Select
OFF
Event action disabled
0
RETRIGGER
Start, restart or re-trigger counter on event
1
COUNTEV
Count on event
2
START
Start counter on event
3
INC
Increment counter on event
4
COUNT
Count on active state of asynchronous event
5
FAULT
Non-recoverable fault
7
EVACT1
Timer/counter Input Event1 Action
3
3
EVACT1Select
OFF
Event action disabled
0
RETRIGGER
Re-trigger counter on event
1
DIR
Direction control
2
STOP
Stop counter on event
3
DEC
Decrement counter on event
4
PPW
Period capture value in CC0 register, pulse width capture value in CC1 register
5
PWP
Period capture value in CC1 register, pulse width capture value in CC0 register
6
FAULT
Non-recoverable fault
7
MCEI0
Match or Capture Channel 0 Event Input Enable
16
1
MCEI1
Match or Capture Channel 1 Event Input Enable
17
1
MCEI2
Match or Capture Channel 2 Event Input Enable
18
1
MCEI3
Match or Capture Channel 3 Event Input Enable
19
1
MCEO0
Match or Capture Channel 0 Event Output Enable
24
1
MCEO1
Match or Capture Channel 1 Event Output Enable
25
1
MCEO2
Match or Capture Channel 2 Event Output Enable
26
1
MCEO3
Match or Capture Channel 3 Event Output Enable
27
1
OVFEO
Overflow/Underflow Output Event Enable
8
1
TCEI0
Timer/counter Event 0 Input Enable
14
1
TCEI1
Timer/counter Event 1 Input Enable
15
1
TCINV0
Inverted Event 0 Input Enable
12
1
TCINV1
Inverted Event 1 Input Enable
13
1
TRGEO
Retrigger Output Event Enable
9
1
FCTRLA
Recoverable Fault A Configuration
0xC
32
read-write
n
0x0
0x0
BLANK
Fault A Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault A Blanking Time
16
8
CAPTURE
Fault A Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault A Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault A Filter Value
24
4
HALT
Fault A Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault A Keeper
3
1
QUAL
Fault A Qualification
4
1
RESTART
Fault A Restart
7
1
SRC
Fault A Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
FCTRLB
Recoverable Fault B Configuration
0x10
32
read-write
n
0x0
0x0
BLANK
Fault B Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault B Blanking Time
16
8
CAPTURE
Fault B Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault B Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault B Filter Value
24
4
HALT
Fault B Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault B Keeper
3
1
QUAL
Fault B Qualification
4
1
RESTART
Fault B Restart
7
1
SRC
Fault B Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
INTENCLR
Interrupt Enable Clear
0x24
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTENSET
Interrupt Enable Set
0x28
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTFLAG
Interrupt Flag Status and Clear
0x2C
32
read-write
n
0x0
0x0
CNT
Counter
2
1
DFS
Non-Recoverable Debug Fault
11
1
ERR
Error
3
1
FAULT0
Non-Recoverable Fault 0
14
1
FAULT1
Non-Recoverable Fault 1
15
1
FAULTA
Recoverable Fault A
12
1
FAULTB
Recoverable Fault B
13
1
MC0
Match or Capture 0
16
1
MC1
Match or Capture 1
17
1
MC2
Match or Capture 2
18
1
MC3
Match or Capture 3
19
1
OVF
Overflow
0
1
TRG
Retrigger
1
1
PATT
Pattern
0x38
16
read-write
n
0x0
0x0
PGE0
Pattern Generator 0 Output Enable
0
1
PGE1
Pattern Generator 1 Output Enable
1
1
PGE2
Pattern Generator 2 Output Enable
2
1
PGE3
Pattern Generator 3 Output Enable
3
1
PGE4
Pattern Generator 4 Output Enable
4
1
PGE5
Pattern Generator 5 Output Enable
5
1
PGE6
Pattern Generator 6 Output Enable
6
1
PGE7
Pattern Generator 7 Output Enable
7
1
PGV0
Pattern Generator 0 Output Value
8
1
PGV1
Pattern Generator 1 Output Value
9
1
PGV2
Pattern Generator 2 Output Value
10
1
PGV3
Pattern Generator 3 Output Value
11
1
PGV4
Pattern Generator 4 Output Value
12
1
PGV5
Pattern Generator 5 Output Value
13
1
PGV6
Pattern Generator 6 Output Value
14
1
PGV7
Pattern Generator 7 Output Value
15
1
PATTB
Pattern Buffer
0x64
16
read-write
n
0x0
0x0
PGEB0
Pattern Generator 0 Output Enable Buffer
0
1
PGEB1
Pattern Generator 1 Output Enable Buffer
1
1
PGEB2
Pattern Generator 2 Output Enable Buffer
2
1
PGEB3
Pattern Generator 3 Output Enable Buffer
3
1
PGEB4
Pattern Generator 4 Output Enable Buffer
4
1
PGEB5
Pattern Generator 5 Output Enable Buffer
5
1
PGEB6
Pattern Generator 6 Output Enable Buffer
6
1
PGEB7
Pattern Generator 7 Output Enable Buffer
7
1
PGVB0
Pattern Generator 0 Output Enable
8
1
PGVB1
Pattern Generator 1 Output Enable
9
1
PGVB2
Pattern Generator 2 Output Enable
10
1
PGVB3
Pattern Generator 3 Output Enable
11
1
PGVB4
Pattern Generator 4 Output Enable
12
1
PGVB5
Pattern Generator 5 Output Enable
13
1
PGVB6
Pattern Generator 6 Output Enable
14
1
PGVB7
Pattern Generator 7 Output Enable
15
1
PER
Period
0x40
32
read-write
n
0x0
0x0
PER
Period Value
0
24
PERB
Period Buffer
0x6C
32
read-write
n
0x0
0x0
PERB
Period Buffer Value
0
24
PERB_DITH4
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH4_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH5
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH5_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH6
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PERB_DITH6_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PER_DITH4
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH4_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH5
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH5_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH6
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
PER_DITH6_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
STATUS
Status
0x30
32
read-write
n
0x0
0x0
CCBV0
Compare Channel 0 Buffer Valid
16
1
CCBV1
Compare Channel 1 Buffer Valid
17
1
CCBV2
Compare Channel 2 Buffer Valid
18
1
CCBV3
Compare Channel 3 Buffer Valid
19
1
CMP0
Compare Channel 0 Value
24
1
read-only
CMP1
Compare Channel 1 Value
25
1
read-only
CMP2
Compare Channel 2 Value
26
1
read-only
CMP3
Compare Channel 3 Value
27
1
read-only
DFS
Non-Recoverable Debug Fault State
3
1
FAULT0
Non-Recoverable Fault 0 State
14
1
FAULT0IN
Non-Recoverable Fault0 Input
10
1
read-only
FAULT1
Non-Recoverable Fault 1 State
15
1
FAULT1IN
Non-Recoverable Fault1 Input
11
1
read-only
FAULTA
Recoverable Fault A State
12
1
FAULTAIN
Recoverable Fault A Input
8
1
read-only
FAULTB
Recoverable Fault B State
13
1
FAULTBIN
Recoverable Fault B Input
9
1
read-only
IDX
Ramp
1
1
read-only
PATTBV
Pattern Buffer Valid
5
1
PERBV
Period Buffer Valid
7
1
SLAVE
Slave
4
1
read-only
STOP
Stop
0
1
read-only
WAVEBV
Wave Buffer Valid
6
1
SYNCBUSY
Synchronization Busy
0x8
32
read-only
n
0x0
0x0
CC0
Compare Channel 0 Busy
8
1
CC1
Compare Channel 1 Busy
9
1
CC2
Compare Channel 2 Busy
10
1
CC3
Compare Channel 3 Busy
11
1
CCB0
Compare Channel Buffer 0 Busy
19
1
CCB1
Compare Channel Buffer 1 Busy
20
1
CCB2
Compare Channel Buffer 2 Busy
21
1
CCB3
Compare Channel Buffer 3 Busy
22
1
COUNT
Count Busy
4
1
CTRLB
Ctrlb Busy
2
1
ENABLE
Enable Busy
1
1
PATT
Pattern Busy
5
1
PATTB
Pattern Buffer Busy
16
1
PER
Period busy
7
1
PERB
Period Buffer Busy
18
1
STATUS
Status Busy
3
1
SWRST
Swrst Busy
0
1
WAVE
Wave Busy
6
1
WAVEB
Wave Buffer Busy
17
1
WAVE
Waveform Control
0x3C
32
read-write
n
0x0
0x0
CICCEN0
Circular Channel 0 Enable
8
1
CICCEN1
Circular Channel 1 Enable
9
1
CICCEN2
Circular Channel 2 Enable
10
1
CICCEN3
Circular Channel 3 Enable
11
1
CIPEREN
Circular period Enable
7
1
POL0
Channel 0 Polarity
16
1
POL1
Channel 1 Polarity
17
1
POL2
Channel 2 Polarity
18
1
POL3
Channel 3 Polarity
19
1
RAMP
Ramp Mode
4
2
RAMPSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAP0
Swap DTI Output Pair 0
24
1
SWAP1
Swap DTI Output Pair 1
25
1
SWAP2
Swap DTI Output Pair 2
26
1
SWAP3
Swap DTI Output Pair 3
27
1
WAVEGEN
Waveform Generation
0
3
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WAVEB
Waveform Control Buffer
0x68
32
read-write
n
0x0
0x0
CICCENB0
Circular Channel 0 Enable Buffer
8
1
CICCENB1
Circular Channel 1 Enable Buffer
9
1
CICCENB2
Circular Channel 2 Enable Buffer
10
1
CICCENB3
Circular Channel 3 Enable Buffer
11
1
CIPERENB
Circular Period Enable Buffer
7
1
POLB0
Channel 0 Polarity Buffer
16
1
POLB1
Channel 1 Polarity Buffer
17
1
POLB2
Channel 2 Polarity Buffer
18
1
POLB3
Channel 3 Polarity Buffer
19
1
RAMPB
Ramp Mode Buffer
4
2
RAMPBSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAPB0
Swap DTI Output Pair 0 Buffer
24
1
SWAPB1
Swap DTI Output Pair 1 Buffer
25
1
SWAPB2
Swap DTI Output Pair 2 Buffer
26
1
SWAPB3
Swap DTI Output Pair 3 Buffer
27
1
WAVEGENB
Waveform Generation Buffer
0
3
WAVEGENBSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WEXCTRL
Waveform Extension Configuration
0x14
32
read-write
n
0x0
0x0
DTHS
Dead-time High Side Outputs Value
24
8
DTIEN0
Dead-time Insertion Generator 0 Enable
8
1
DTIEN1
Dead-time Insertion Generator 1 Enable
9
1
DTIEN2
Dead-time Insertion Generator 2 Enable
10
1
DTIEN3
Dead-time Insertion Generator 3 Enable
11
1
DTLS
Dead-time Low Side Outputs Value
16
8
OTMX
Output Matrix
0
2
TCC1
Timer Counter Control
TCC
0x0
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
TCC1_INTREQ
16
CC0
Compare and Capture
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC0_DITH4
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC0_DITH5
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC0_DITH6
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC1
Compare and Capture
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC1_DITH4
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC1_DITH5
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC1_DITH6
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC2
Compare and Capture
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC2_DITH4
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC2_DITH5
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC2_DITH6
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC3
Compare and Capture
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC3_DITH4
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC3_DITH5
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC3_DITH6
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CCB0
Compare and Capture Buffer
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB0_DITH4
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB0_DITH5
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB0_DITH6
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB1
Compare and Capture Buffer
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB1_DITH4
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB1_DITH5
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB1_DITH6
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB2
Compare and Capture Buffer
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB2_DITH4
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB2_DITH5
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB2_DITH6
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB3
Compare and Capture Buffer
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB3_DITH4
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB3_DITH5
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB3_DITH6
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH4_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH5_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH6_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CC_DITH4_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH5_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH6_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
COUNT
Count
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
24
COUNT_DITH4
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH4_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH5
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH5_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH6
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
COUNT_DITH6_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
14
1
CPTEN0
Capture Channel 0 Enable
24
1
CPTEN1
Capture Channel 1 Enable
25
1
CPTEN2
Capture Channel 2 Enable
26
1
CPTEN3
Capture Channel 3 Enable
27
1
ENABLE
Enable
1
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
No division
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV64
Divide by 64
5
DIV256
Divide by 256
6
DIV1024
Divide by 1024
7
PRESCSYNC
Prescaler and Counter Synchronization Selection
12
2
PRESCSYNCSelect
GCLK
Reload or reset counter on next GCLK
0
PRESC
Reload or reset counter on next prescaler clock
1
RESYNC
Reload or reset counter on next GCLK and reset prescaler counter
2
RESOLUTION
Enhanced Resolution
5
2
RESOLUTIONSelect
NONE
Dithering is disabled
0
DITH4
Dithering is done every 16 PWM frames
1
DITH5
Dithering is done every 32 PWM frames
2
DITH6
Dithering is done every 64 PWM frames
3
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
DBGCTRL
Debug Control
0x1E
8
read-write
n
0x0
0x0
DBGRUN
Debug Running Mode
0
1
FDDBD
Fault Detection on Debug Break Detection
2
1
DRVCTRL
Driver Control
0x18
32
read-write
n
0x0
0x0
FILTERVAL0
Non-Recoverable Fault Input 0 Filter Value
24
4
FILTERVAL1
Non-Recoverable Fault Input 1 Filter Value
28
4
INVEN0
Output Waveform 0 Inversion
16
1
INVEN1
Output Waveform 1 Inversion
17
1
INVEN2
Output Waveform 2 Inversion
18
1
INVEN3
Output Waveform 3 Inversion
19
1
INVEN4
Output Waveform 4 Inversion
20
1
INVEN5
Output Waveform 5 Inversion
21
1
INVEN6
Output Waveform 6 Inversion
22
1
INVEN7
Output Waveform 7 Inversion
23
1
NRE0
Non-Recoverable State 0 Output Enable
0
1
NRE1
Non-Recoverable State 1 Output Enable
1
1
NRE2
Non-Recoverable State 2 Output Enable
2
1
NRE3
Non-Recoverable State 3 Output Enable
3
1
NRE4
Non-Recoverable State 4 Output Enable
4
1
NRE5
Non-Recoverable State 5 Output Enable
5
1
NRE6
Non-Recoverable State 6 Output Enable
6
1
NRE7
Non-Recoverable State 7 Output Enable
7
1
NRV0
Non-Recoverable State 0 Output Value
8
1
NRV1
Non-Recoverable State 1 Output Value
9
1
NRV2
Non-Recoverable State 2 Output Value
10
1
NRV3
Non-Recoverable State 3 Output Value
11
1
NRV4
Non-Recoverable State 4 Output Value
12
1
NRV5
Non-Recoverable State 5 Output Value
13
1
NRV6
Non-Recoverable State 6 Output Value
14
1
NRV7
Non-Recoverable State 7 Output Value
15
1
EVCTRL
Event Control
0x20
32
read-write
n
0x0
0x0
CNTEO
Timer/counter Output Event Enable
10
1
CNTSEL
Timer/counter Output Event Mode
6
2
CNTSELSelect
START
An interrupt/event is generated when a new counter cycle starts
0
END
An interrupt/event is generated when a counter cycle ends
1
BETWEEN
An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
2
BOUNDARY
An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
3
EVACT0
Timer/counter Input Event0 Action
0
3
EVACT0Select
OFF
Event action disabled
0
RETRIGGER
Start, restart or re-trigger counter on event
1
COUNTEV
Count on event
2
START
Start counter on event
3
INC
Increment counter on event
4
COUNT
Count on active state of asynchronous event
5
FAULT
Non-recoverable fault
7
EVACT1
Timer/counter Input Event1 Action
3
3
EVACT1Select
OFF
Event action disabled
0
RETRIGGER
Re-trigger counter on event
1
DIR
Direction control
2
STOP
Stop counter on event
3
DEC
Decrement counter on event
4
PPW
Period capture value in CC0 register, pulse width capture value in CC1 register
5
PWP
Period capture value in CC1 register, pulse width capture value in CC0 register
6
FAULT
Non-recoverable fault
7
MCEI0
Match or Capture Channel 0 Event Input Enable
16
1
MCEI1
Match or Capture Channel 1 Event Input Enable
17
1
MCEI2
Match or Capture Channel 2 Event Input Enable
18
1
MCEI3
Match or Capture Channel 3 Event Input Enable
19
1
MCEO0
Match or Capture Channel 0 Event Output Enable
24
1
MCEO1
Match or Capture Channel 1 Event Output Enable
25
1
MCEO2
Match or Capture Channel 2 Event Output Enable
26
1
MCEO3
Match or Capture Channel 3 Event Output Enable
27
1
OVFEO
Overflow/Underflow Output Event Enable
8
1
TCEI0
Timer/counter Event 0 Input Enable
14
1
TCEI1
Timer/counter Event 1 Input Enable
15
1
TCINV0
Inverted Event 0 Input Enable
12
1
TCINV1
Inverted Event 1 Input Enable
13
1
TRGEO
Retrigger Output Event Enable
9
1
FCTRLA
Recoverable Fault A Configuration
0xC
32
read-write
n
0x0
0x0
BLANK
Fault A Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault A Blanking Time
16
8
CAPTURE
Fault A Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault A Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault A Filter Value
24
4
HALT
Fault A Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault A Keeper
3
1
QUAL
Fault A Qualification
4
1
RESTART
Fault A Restart
7
1
SRC
Fault A Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
FCTRLB
Recoverable Fault B Configuration
0x10
32
read-write
n
0x0
0x0
BLANK
Fault B Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault B Blanking Time
16
8
CAPTURE
Fault B Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault B Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault B Filter Value
24
4
HALT
Fault B Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault B Keeper
3
1
QUAL
Fault B Qualification
4
1
RESTART
Fault B Restart
7
1
SRC
Fault B Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
INTENCLR
Interrupt Enable Clear
0x24
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTENSET
Interrupt Enable Set
0x28
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTFLAG
Interrupt Flag Status and Clear
0x2C
32
read-write
n
0x0
0x0
CNT
Counter
2
1
DFS
Non-Recoverable Debug Fault
11
1
ERR
Error
3
1
FAULT0
Non-Recoverable Fault 0
14
1
FAULT1
Non-Recoverable Fault 1
15
1
FAULTA
Recoverable Fault A
12
1
FAULTB
Recoverable Fault B
13
1
MC0
Match or Capture 0
16
1
MC1
Match or Capture 1
17
1
MC2
Match or Capture 2
18
1
MC3
Match or Capture 3
19
1
OVF
Overflow
0
1
TRG
Retrigger
1
1
PATT
Pattern
0x38
16
read-write
n
0x0
0x0
PGE0
Pattern Generator 0 Output Enable
0
1
PGE1
Pattern Generator 1 Output Enable
1
1
PGE2
Pattern Generator 2 Output Enable
2
1
PGE3
Pattern Generator 3 Output Enable
3
1
PGE4
Pattern Generator 4 Output Enable
4
1
PGE5
Pattern Generator 5 Output Enable
5
1
PGE6
Pattern Generator 6 Output Enable
6
1
PGE7
Pattern Generator 7 Output Enable
7
1
PGV0
Pattern Generator 0 Output Value
8
1
PGV1
Pattern Generator 1 Output Value
9
1
PGV2
Pattern Generator 2 Output Value
10
1
PGV3
Pattern Generator 3 Output Value
11
1
PGV4
Pattern Generator 4 Output Value
12
1
PGV5
Pattern Generator 5 Output Value
13
1
PGV6
Pattern Generator 6 Output Value
14
1
PGV7
Pattern Generator 7 Output Value
15
1
PATTB
Pattern Buffer
0x64
16
read-write
n
0x0
0x0
PGEB0
Pattern Generator 0 Output Enable Buffer
0
1
PGEB1
Pattern Generator 1 Output Enable Buffer
1
1
PGEB2
Pattern Generator 2 Output Enable Buffer
2
1
PGEB3
Pattern Generator 3 Output Enable Buffer
3
1
PGEB4
Pattern Generator 4 Output Enable Buffer
4
1
PGEB5
Pattern Generator 5 Output Enable Buffer
5
1
PGEB6
Pattern Generator 6 Output Enable Buffer
6
1
PGEB7
Pattern Generator 7 Output Enable Buffer
7
1
PGVB0
Pattern Generator 0 Output Enable
8
1
PGVB1
Pattern Generator 1 Output Enable
9
1
PGVB2
Pattern Generator 2 Output Enable
10
1
PGVB3
Pattern Generator 3 Output Enable
11
1
PGVB4
Pattern Generator 4 Output Enable
12
1
PGVB5
Pattern Generator 5 Output Enable
13
1
PGVB6
Pattern Generator 6 Output Enable
14
1
PGVB7
Pattern Generator 7 Output Enable
15
1
PER
Period
0x40
32
read-write
n
0x0
0x0
PER
Period Value
0
24
PERB
Period Buffer
0x6C
32
read-write
n
0x0
0x0
PERB
Period Buffer Value
0
24
PERB_DITH4
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH4_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH5
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH5_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH6
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PERB_DITH6_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PER_DITH4
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH4_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH5
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH5_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH6
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
PER_DITH6_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
STATUS
Status
0x30
32
read-write
n
0x0
0x0
CCBV0
Compare Channel 0 Buffer Valid
16
1
CCBV1
Compare Channel 1 Buffer Valid
17
1
CCBV2
Compare Channel 2 Buffer Valid
18
1
CCBV3
Compare Channel 3 Buffer Valid
19
1
CMP0
Compare Channel 0 Value
24
1
read-only
CMP1
Compare Channel 1 Value
25
1
read-only
CMP2
Compare Channel 2 Value
26
1
read-only
CMP3
Compare Channel 3 Value
27
1
read-only
DFS
Non-Recoverable Debug Fault State
3
1
FAULT0
Non-Recoverable Fault 0 State
14
1
FAULT0IN
Non-Recoverable Fault0 Input
10
1
read-only
FAULT1
Non-Recoverable Fault 1 State
15
1
FAULT1IN
Non-Recoverable Fault1 Input
11
1
read-only
FAULTA
Recoverable Fault A State
12
1
FAULTAIN
Recoverable Fault A Input
8
1
read-only
FAULTB
Recoverable Fault B State
13
1
FAULTBIN
Recoverable Fault B Input
9
1
read-only
IDX
Ramp
1
1
read-only
PATTBV
Pattern Buffer Valid
5
1
PERBV
Period Buffer Valid
7
1
SLAVE
Slave
4
1
read-only
STOP
Stop
0
1
read-only
WAVEBV
Wave Buffer Valid
6
1
SYNCBUSY
Synchronization Busy
0x8
32
read-only
n
0x0
0x0
CC0
Compare Channel 0 Busy
8
1
CC1
Compare Channel 1 Busy
9
1
CC2
Compare Channel 2 Busy
10
1
CC3
Compare Channel 3 Busy
11
1
CCB0
Compare Channel Buffer 0 Busy
19
1
CCB1
Compare Channel Buffer 1 Busy
20
1
CCB2
Compare Channel Buffer 2 Busy
21
1
CCB3
Compare Channel Buffer 3 Busy
22
1
COUNT
Count Busy
4
1
CTRLB
Ctrlb Busy
2
1
ENABLE
Enable Busy
1
1
PATT
Pattern Busy
5
1
PATTB
Pattern Buffer Busy
16
1
PER
Period busy
7
1
PERB
Period Buffer Busy
18
1
STATUS
Status Busy
3
1
SWRST
Swrst Busy
0
1
WAVE
Wave Busy
6
1
WAVEB
Wave Buffer Busy
17
1
WAVE
Waveform Control
0x3C
32
read-write
n
0x0
0x0
CICCEN0
Circular Channel 0 Enable
8
1
CICCEN1
Circular Channel 1 Enable
9
1
CICCEN2
Circular Channel 2 Enable
10
1
CICCEN3
Circular Channel 3 Enable
11
1
CIPEREN
Circular period Enable
7
1
POL0
Channel 0 Polarity
16
1
POL1
Channel 1 Polarity
17
1
POL2
Channel 2 Polarity
18
1
POL3
Channel 3 Polarity
19
1
RAMP
Ramp Mode
4
2
RAMPSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAP0
Swap DTI Output Pair 0
24
1
SWAP1
Swap DTI Output Pair 1
25
1
SWAP2
Swap DTI Output Pair 2
26
1
SWAP3
Swap DTI Output Pair 3
27
1
WAVEGEN
Waveform Generation
0
3
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WAVEB
Waveform Control Buffer
0x68
32
read-write
n
0x0
0x0
CICCENB0
Circular Channel 0 Enable Buffer
8
1
CICCENB1
Circular Channel 1 Enable Buffer
9
1
CICCENB2
Circular Channel 2 Enable Buffer
10
1
CICCENB3
Circular Channel 3 Enable Buffer
11
1
CIPERENB
Circular Period Enable Buffer
7
1
POLB0
Channel 0 Polarity Buffer
16
1
POLB1
Channel 1 Polarity Buffer
17
1
POLB2
Channel 2 Polarity Buffer
18
1
POLB3
Channel 3 Polarity Buffer
19
1
RAMPB
Ramp Mode Buffer
4
2
RAMPBSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAPB0
Swap DTI Output Pair 0 Buffer
24
1
SWAPB1
Swap DTI Output Pair 1 Buffer
25
1
SWAPB2
Swap DTI Output Pair 2 Buffer
26
1
SWAPB3
Swap DTI Output Pair 3 Buffer
27
1
WAVEGENB
Waveform Generation Buffer
0
3
WAVEGENBSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WEXCTRL
Waveform Extension Configuration
0x14
32
read-write
n
0x0
0x0
DTHS
Dead-time High Side Outputs Value
24
8
DTIEN0
Dead-time Insertion Generator 0 Enable
8
1
DTIEN1
Dead-time Insertion Generator 1 Enable
9
1
DTIEN2
Dead-time Insertion Generator 2 Enable
10
1
DTIEN3
Dead-time Insertion Generator 3 Enable
11
1
DTLS
Dead-time Low Side Outputs Value
16
8
OTMX
Output Matrix
0
2
TCC2
Timer Counter Control
TCC
0x0
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
0x0
0x80
registers
n
TCC2_INTREQ
17
CC0
Compare and Capture
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC0_DITH4
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC0_DITH5
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC0_DITH6
Compare and Capture
CC%s
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC1
Compare and Capture
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC1_DITH4
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC1_DITH5
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC1_DITH6
Compare and Capture
CC%s
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC2
Compare and Capture
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC2_DITH4
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC2_DITH5
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC2_DITH6
Compare and Capture
CC%s
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC3
Compare and Capture
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
0
24
CC3_DITH4
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC3_DITH5
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC3_DITH6
Compare and Capture
CC%s
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CCB0
Compare and Capture Buffer
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB0_DITH4
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB0_DITH5
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB0_DITH6
Compare and Capture Buffer
CCB%s
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB1
Compare and Capture Buffer
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB1_DITH4
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB1_DITH5
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB1_DITH6
Compare and Capture Buffer
CCB%s
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB2
Compare and Capture Buffer
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB2_DITH4
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB2_DITH5
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB2_DITH6
Compare and Capture Buffer
CCB%s
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB3
Compare and Capture Buffer
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
0
24
CCB3_DITH4
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB3_DITH5
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB3_DITH6
Compare and Capture Buffer
CCB%s
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH4_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH4_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
4
20
DITHERCYB
Dithering Buffer Cycle Number
0
4
CCB_DITH5_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH5_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
5
19
DITHERCYB
Dithering Buffer Cycle Number
0
5
CCB_DITH6_MODE0
Compare and Capture Buffer
CCB[%s]
0x70
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE1
Compare and Capture Buffer
CCB[%s]
0x74
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE2
Compare and Capture Buffer
CCB[%s]
0x78
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CCB_DITH6_MODE3
Compare and Capture Buffer
CCB[%s]
0x7C
32
read-write
n
0x0
0x0
CCB
Channel Compare/Capture Buffer Value
6
18
DITHERCYB
Dithering Buffer Cycle Number
0
6
CC_DITH4_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH4_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
4
20
DITHERCY
Dithering Cycle Number
0
4
CC_DITH5_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH5_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
5
19
DITHERCY
Dithering Cycle Number
0
5
CC_DITH6_MODE0
Compare and Capture
CC[%s]
0x44
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE1
Compare and Capture
CC[%s]
0x48
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE2
Compare and Capture
CC[%s]
0x4C
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
CC_DITH6_MODE3
Compare and Capture
CC[%s]
0x50
32
read-write
n
0x0
0x0
CC
Channel Compare/Capture Value
6
18
DITHERCY
Dithering Cycle Number
0
6
COUNT
Count
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
24
COUNT_DITH4
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH4_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
4
20
COUNT_DITH5
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH5_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
5
19
COUNT_DITH6
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
COUNT_DITH6_MODE
Count
COUNT
0x34
32
read-write
n
0x0
0x0
COUNT
Counter Value
6
18
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
14
1
CPTEN0
Capture Channel 0 Enable
24
1
CPTEN1
Capture Channel 1 Enable
25
1
CPTEN2
Capture Channel 2 Enable
26
1
CPTEN3
Capture Channel 3 Enable
27
1
ENABLE
Enable
1
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
No division
0
DIV2
Divide by 2
1
DIV4
Divide by 4
2
DIV8
Divide by 8
3
DIV16
Divide by 16
4
DIV64
Divide by 64
5
DIV256
Divide by 256
6
DIV1024
Divide by 1024
7
PRESCSYNC
Prescaler and Counter Synchronization Selection
12
2
PRESCSYNCSelect
GCLK
Reload or reset counter on next GCLK
0
PRESC
Reload or reset counter on next prescaler clock
1
RESYNC
Reload or reset counter on next GCLK and reset prescaler counter
2
RESOLUTION
Enhanced Resolution
5
2
RESOLUTIONSelect
NONE
Dithering is disabled
0
DITH4
Dithering is done every 16 PWM frames
1
DITH5
Dithering is done every 32 PWM frames
2
DITH6
Dithering is done every 64 PWM frames
3
RUNSTDBY
Run in Standby
11
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
TCC Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Clear start, restart or retrigger
1
STOP
Force stop
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force COUNT read synchronization
4
DIR
Counter Direction
0
1
IDXCMD
Ramp Index Command
3
2
IDXCMDSelect
DISABLE
Command disabled: Index toggles between cycles A and B
0
SET
Set index: cycle B will be forced in the next cycle
1
CLEAR
Clear index: cycle A will be forced in the next cycle
2
HOLD
Hold index: the next cycle will be the same as the current cycle
3
LUPD
Lock Update
1
1
ONESHOT
One-Shot
2
1
DBGCTRL
Debug Control
0x1E
8
read-write
n
0x0
0x0
DBGRUN
Debug Running Mode
0
1
FDDBD
Fault Detection on Debug Break Detection
2
1
DRVCTRL
Driver Control
0x18
32
read-write
n
0x0
0x0
FILTERVAL0
Non-Recoverable Fault Input 0 Filter Value
24
4
FILTERVAL1
Non-Recoverable Fault Input 1 Filter Value
28
4
INVEN0
Output Waveform 0 Inversion
16
1
INVEN1
Output Waveform 1 Inversion
17
1
INVEN2
Output Waveform 2 Inversion
18
1
INVEN3
Output Waveform 3 Inversion
19
1
INVEN4
Output Waveform 4 Inversion
20
1
INVEN5
Output Waveform 5 Inversion
21
1
INVEN6
Output Waveform 6 Inversion
22
1
INVEN7
Output Waveform 7 Inversion
23
1
NRE0
Non-Recoverable State 0 Output Enable
0
1
NRE1
Non-Recoverable State 1 Output Enable
1
1
NRE2
Non-Recoverable State 2 Output Enable
2
1
NRE3
Non-Recoverable State 3 Output Enable
3
1
NRE4
Non-Recoverable State 4 Output Enable
4
1
NRE5
Non-Recoverable State 5 Output Enable
5
1
NRE6
Non-Recoverable State 6 Output Enable
6
1
NRE7
Non-Recoverable State 7 Output Enable
7
1
NRV0
Non-Recoverable State 0 Output Value
8
1
NRV1
Non-Recoverable State 1 Output Value
9
1
NRV2
Non-Recoverable State 2 Output Value
10
1
NRV3
Non-Recoverable State 3 Output Value
11
1
NRV4
Non-Recoverable State 4 Output Value
12
1
NRV5
Non-Recoverable State 5 Output Value
13
1
NRV6
Non-Recoverable State 6 Output Value
14
1
NRV7
Non-Recoverable State 7 Output Value
15
1
EVCTRL
Event Control
0x20
32
read-write
n
0x0
0x0
CNTEO
Timer/counter Output Event Enable
10
1
CNTSEL
Timer/counter Output Event Mode
6
2
CNTSELSelect
START
An interrupt/event is generated when a new counter cycle starts
0
END
An interrupt/event is generated when a counter cycle ends
1
BETWEEN
An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
2
BOUNDARY
An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
3
EVACT0
Timer/counter Input Event0 Action
0
3
EVACT0Select
OFF
Event action disabled
0
RETRIGGER
Start, restart or re-trigger counter on event
1
COUNTEV
Count on event
2
START
Start counter on event
3
INC
Increment counter on event
4
COUNT
Count on active state of asynchronous event
5
FAULT
Non-recoverable fault
7
EVACT1
Timer/counter Input Event1 Action
3
3
EVACT1Select
OFF
Event action disabled
0
RETRIGGER
Re-trigger counter on event
1
DIR
Direction control
2
STOP
Stop counter on event
3
DEC
Decrement counter on event
4
PPW
Period capture value in CC0 register, pulse width capture value in CC1 register
5
PWP
Period capture value in CC1 register, pulse width capture value in CC0 register
6
FAULT
Non-recoverable fault
7
MCEI0
Match or Capture Channel 0 Event Input Enable
16
1
MCEI1
Match or Capture Channel 1 Event Input Enable
17
1
MCEI2
Match or Capture Channel 2 Event Input Enable
18
1
MCEI3
Match or Capture Channel 3 Event Input Enable
19
1
MCEO0
Match or Capture Channel 0 Event Output Enable
24
1
MCEO1
Match or Capture Channel 1 Event Output Enable
25
1
MCEO2
Match or Capture Channel 2 Event Output Enable
26
1
MCEO3
Match or Capture Channel 3 Event Output Enable
27
1
OVFEO
Overflow/Underflow Output Event Enable
8
1
TCEI0
Timer/counter Event 0 Input Enable
14
1
TCEI1
Timer/counter Event 1 Input Enable
15
1
TCINV0
Inverted Event 0 Input Enable
12
1
TCINV1
Inverted Event 1 Input Enable
13
1
TRGEO
Retrigger Output Event Enable
9
1
FCTRLA
Recoverable Fault A Configuration
0xC
32
read-write
n
0x0
0x0
BLANK
Fault A Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault A Blanking Time
16
8
CAPTURE
Fault A Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault A Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault A Filter Value
24
4
HALT
Fault A Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault A Keeper
3
1
QUAL
Fault A Qualification
4
1
RESTART
Fault A Restart
7
1
SRC
Fault A Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
FCTRLB
Recoverable Fault B Configuration
0x10
32
read-write
n
0x0
0x0
BLANK
Fault B Blanking Mode
5
2
BLANKSelect
NONE
No blanking applied
0
RISE
Blanking applied from rising edge of the output waveform
1
FALL
Blanking applied from falling edge of the output waveform
2
BOTH
Blanking applied from each toggle of the output waveform
3
BLANKVAL
Fault B Blanking Time
16
8
CAPTURE
Fault B Capture Action
12
3
CAPTURESelect
DISABLE
No capture
0
CAPT
Capture on fault
1
CAPTMIN
Minimum capture
2
CAPTMAX
Maximum capture
3
LOCMIN
Minimum local detection
4
LOCMAX
Maximum local detection
5
DERIV0
Minimum and maximum local detection
6
CHSEL
Fault B Capture Channel
10
2
CHSELSelect
CC0
Capture value stored in channel 0
0
CC1
Capture value stored in channel 1
1
CC2
Capture value stored in channel 2
2
CC3
Capture value stored in channel 3
3
FILTERVAL
Fault B Filter Value
24
4
HALT
Fault B Halt Mode
8
2
HALTSelect
DISABLE
Halt action disabled
0
HW
Hardware halt action
1
SW
Software halt action
2
NR
Non-recoverable fault
3
KEEP
Fault B Keeper
3
1
QUAL
Fault B Qualification
4
1
RESTART
Fault B Restart
7
1
SRC
Fault B Source
0
2
SRCSelect
DISABLE
Fault input disabled
0
ENABLE
MCEx (x=0,1) event input
1
INVERT
Inverted MCEx (x=0,1) event input
2
ALTFAULT
Alternate fault (A or B) state at the end of the previous period
3
INTENCLR
Interrupt Enable Clear
0x24
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTENSET
Interrupt Enable Set
0x28
32
read-write
n
0x0
0x0
CNT
Counter Interrupt Enable
2
1
DFS
Non-Recoverable Debug Fault Interrupt Enable
11
1
ERR
Error Interrupt Enable
3
1
FAULT0
Non-Recoverable Fault 0 Interrupt Enable
14
1
FAULT1
Non-Recoverable Fault 1 Interrupt Enable
15
1
FAULTA
Recoverable Fault A Interrupt Enable
12
1
FAULTB
Recoverable Fault B Interrupt Enable
13
1
MC0
Match or Capture Channel 0 Interrupt Enable
16
1
MC1
Match or Capture Channel 1 Interrupt Enable
17
1
MC2
Match or Capture Channel 2 Interrupt Enable
18
1
MC3
Match or Capture Channel 3 Interrupt Enable
19
1
OVF
Overflow Interrupt Enable
0
1
TRG
Retrigger Interrupt Enable
1
1
INTFLAG
Interrupt Flag Status and Clear
0x2C
32
read-write
n
0x0
0x0
CNT
Counter
2
1
DFS
Non-Recoverable Debug Fault
11
1
ERR
Error
3
1
FAULT0
Non-Recoverable Fault 0
14
1
FAULT1
Non-Recoverable Fault 1
15
1
FAULTA
Recoverable Fault A
12
1
FAULTB
Recoverable Fault B
13
1
MC0
Match or Capture 0
16
1
MC1
Match or Capture 1
17
1
MC2
Match or Capture 2
18
1
MC3
Match or Capture 3
19
1
OVF
Overflow
0
1
TRG
Retrigger
1
1
PATT
Pattern
0x38
16
read-write
n
0x0
0x0
PGE0
Pattern Generator 0 Output Enable
0
1
PGE1
Pattern Generator 1 Output Enable
1
1
PGE2
Pattern Generator 2 Output Enable
2
1
PGE3
Pattern Generator 3 Output Enable
3
1
PGE4
Pattern Generator 4 Output Enable
4
1
PGE5
Pattern Generator 5 Output Enable
5
1
PGE6
Pattern Generator 6 Output Enable
6
1
PGE7
Pattern Generator 7 Output Enable
7
1
PGV0
Pattern Generator 0 Output Value
8
1
PGV1
Pattern Generator 1 Output Value
9
1
PGV2
Pattern Generator 2 Output Value
10
1
PGV3
Pattern Generator 3 Output Value
11
1
PGV4
Pattern Generator 4 Output Value
12
1
PGV5
Pattern Generator 5 Output Value
13
1
PGV6
Pattern Generator 6 Output Value
14
1
PGV7
Pattern Generator 7 Output Value
15
1
PATTB
Pattern Buffer
0x64
16
read-write
n
0x0
0x0
PGEB0
Pattern Generator 0 Output Enable Buffer
0
1
PGEB1
Pattern Generator 1 Output Enable Buffer
1
1
PGEB2
Pattern Generator 2 Output Enable Buffer
2
1
PGEB3
Pattern Generator 3 Output Enable Buffer
3
1
PGEB4
Pattern Generator 4 Output Enable Buffer
4
1
PGEB5
Pattern Generator 5 Output Enable Buffer
5
1
PGEB6
Pattern Generator 6 Output Enable Buffer
6
1
PGEB7
Pattern Generator 7 Output Enable Buffer
7
1
PGVB0
Pattern Generator 0 Output Enable
8
1
PGVB1
Pattern Generator 1 Output Enable
9
1
PGVB2
Pattern Generator 2 Output Enable
10
1
PGVB3
Pattern Generator 3 Output Enable
11
1
PGVB4
Pattern Generator 4 Output Enable
12
1
PGVB5
Pattern Generator 5 Output Enable
13
1
PGVB6
Pattern Generator 6 Output Enable
14
1
PGVB7
Pattern Generator 7 Output Enable
15
1
PER
Period
0x40
32
read-write
n
0x0
0x0
PER
Period Value
0
24
PERB
Period Buffer
0x6C
32
read-write
n
0x0
0x0
PERB
Period Buffer Value
0
24
PERB_DITH4
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH4_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
4
PERB
Period Buffer Value
4
20
PERB_DITH5
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH5_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
5
PERB
Period Buffer Value
5
19
PERB_DITH6
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PERB_DITH6_MODE
Period Buffer
PERB
0x6C
32
read-write
n
0x0
0x0
DITHERCYB
Dithering Buffer Cycle Number
0
6
PERB
Period Buffer Value
6
18
PER_DITH4
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH4_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
4
PER
Period Value
4
20
PER_DITH5
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH5_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
5
PER
Period Value
5
19
PER_DITH6
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
PER_DITH6_MODE
Period
PER
0x40
32
read-write
n
0x0
0x0
DITHERCY
Dithering Cycle Number
0
6
PER
Period Value
6
18
STATUS
Status
0x30
32
read-write
n
0x0
0x0
CCBV0
Compare Channel 0 Buffer Valid
16
1
CCBV1
Compare Channel 1 Buffer Valid
17
1
CCBV2
Compare Channel 2 Buffer Valid
18
1
CCBV3
Compare Channel 3 Buffer Valid
19
1
CMP0
Compare Channel 0 Value
24
1
read-only
CMP1
Compare Channel 1 Value
25
1
read-only
CMP2
Compare Channel 2 Value
26
1
read-only
CMP3
Compare Channel 3 Value
27
1
read-only
DFS
Non-Recoverable Debug Fault State
3
1
FAULT0
Non-Recoverable Fault 0 State
14
1
FAULT0IN
Non-Recoverable Fault0 Input
10
1
read-only
FAULT1
Non-Recoverable Fault 1 State
15
1
FAULT1IN
Non-Recoverable Fault1 Input
11
1
read-only
FAULTA
Recoverable Fault A State
12
1
FAULTAIN
Recoverable Fault A Input
8
1
read-only
FAULTB
Recoverable Fault B State
13
1
FAULTBIN
Recoverable Fault B Input
9
1
read-only
IDX
Ramp
1
1
read-only
PATTBV
Pattern Buffer Valid
5
1
PERBV
Period Buffer Valid
7
1
SLAVE
Slave
4
1
read-only
STOP
Stop
0
1
read-only
WAVEBV
Wave Buffer Valid
6
1
SYNCBUSY
Synchronization Busy
0x8
32
read-only
n
0x0
0x0
CC0
Compare Channel 0 Busy
8
1
CC1
Compare Channel 1 Busy
9
1
CC2
Compare Channel 2 Busy
10
1
CC3
Compare Channel 3 Busy
11
1
CCB0
Compare Channel Buffer 0 Busy
19
1
CCB1
Compare Channel Buffer 1 Busy
20
1
CCB2
Compare Channel Buffer 2 Busy
21
1
CCB3
Compare Channel Buffer 3 Busy
22
1
COUNT
Count Busy
4
1
CTRLB
Ctrlb Busy
2
1
ENABLE
Enable Busy
1
1
PATT
Pattern Busy
5
1
PATTB
Pattern Buffer Busy
16
1
PER
Period busy
7
1
PERB
Period Buffer Busy
18
1
STATUS
Status Busy
3
1
SWRST
Swrst Busy
0
1
WAVE
Wave Busy
6
1
WAVEB
Wave Buffer Busy
17
1
WAVE
Waveform Control
0x3C
32
read-write
n
0x0
0x0
CICCEN0
Circular Channel 0 Enable
8
1
CICCEN1
Circular Channel 1 Enable
9
1
CICCEN2
Circular Channel 2 Enable
10
1
CICCEN3
Circular Channel 3 Enable
11
1
CIPEREN
Circular period Enable
7
1
POL0
Channel 0 Polarity
16
1
POL1
Channel 1 Polarity
17
1
POL2
Channel 2 Polarity
18
1
POL3
Channel 3 Polarity
19
1
RAMP
Ramp Mode
4
2
RAMPSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAP0
Swap DTI Output Pair 0
24
1
SWAP1
Swap DTI Output Pair 1
25
1
SWAP2
Swap DTI Output Pair 2
26
1
SWAP3
Swap DTI Output Pair 3
27
1
WAVEGEN
Waveform Generation
0
3
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WAVEB
Waveform Control Buffer
0x68
32
read-write
n
0x0
0x0
CICCENB0
Circular Channel 0 Enable Buffer
8
1
CICCENB1
Circular Channel 1 Enable Buffer
9
1
CICCENB2
Circular Channel 2 Enable Buffer
10
1
CICCENB3
Circular Channel 3 Enable Buffer
11
1
CIPERENB
Circular Period Enable Buffer
7
1
POLB0
Channel 0 Polarity Buffer
16
1
POLB1
Channel 1 Polarity Buffer
17
1
POLB2
Channel 2 Polarity Buffer
18
1
POLB3
Channel 3 Polarity Buffer
19
1
RAMPB
Ramp Mode Buffer
4
2
RAMPBSelect
RAMP1
RAMP1 operation
0
RAMP2A
Alternative RAMP2 operation
1
RAMP2
RAMP2 operation
2
SWAPB0
Swap DTI Output Pair 0 Buffer
24
1
SWAPB1
Swap DTI Output Pair 1 Buffer
25
1
SWAPB2
Swap DTI Output Pair 2 Buffer
26
1
SWAPB3
Swap DTI Output Pair 3 Buffer
27
1
WAVEGENB
Waveform Generation Buffer
0
3
WAVEGENBSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
DSCRITICAL
Dual-slope critical
4
DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
5
DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
6
DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
7
WEXCTRL
Waveform Extension Configuration
0x14
32
read-write
n
0x0
0x0
DTHS
Dead-time High Side Outputs Value
24
8
DTIEN0
Dead-time Insertion Generator 0 Enable
8
1
DTIEN1
Dead-time Insertion Generator 1 Enable
9
1
DTIEN2
Dead-time Insertion Generator 2 Enable
10
1
DTIEN3
Dead-time Insertion Generator 3 Enable
11
1
DTLS
Dead-time Low Side Outputs Value
16
8
OTMX
Output Matrix
0
2
USB
Universal Serial Bus
USB
0x0
0x0
0x200
registers
n
0x0
0x200
registers
n
0x0
0x200
registers
n
0x0
0x200
registers
n
USB_INTREQ
7
USB
7
BINTERVAL
HOST_PIPE Bus Access Period of Pipe
0x3
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL0
HOST Bus Access Period of Pipe
0x103
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL1
HOST Bus Access Period of Pipe
0x123
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL2
HOST Bus Access Period of Pipe
0x143
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL3
HOST Bus Access Period of Pipe
0x163
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL4
HOST Bus Access Period of Pipe
0x183
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL5
HOST Bus Access Period of Pipe
0x1A3
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL6
HOST Bus Access Period of Pipe
0x1C3
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
BINTERVAL7
HOST Bus Access Period of Pipe
0x1E3
8
read-write
n
0x0
0x0
BITINTERVAL
Bit Interval
0
8
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
MODE
Operating Mode
7
1
MODESelect
DEVICE
Device Mode
0
HOST
Host Mode
1
RUNSTDBY
Run in Standby Mode
2
1
SWRST
Software Reset
0
1
CTRLB
HOST Control B
0x8
16
read-write
n
0x0
0x0
BUSRESET
Send USB Reset
9
1
DETACH
Detach
0
1
GNAK
Global NAK
9
1
L1RESUME
Send L1 Resume
11
1
LPMHDSK
Link Power Management Handshake
10
2
LPMHDSKSelect
NO
No handshake. LPM is not supported
0
ACK
ACK
1
NYET
NYET
2
STALL
STALL
3
NREPLY
No Reply
4
1
OPMODE2
Specific Operational Mode
8
1
RESUME
Send USB Resume
1
1
SOFE
Start of Frame Generation Enable
8
1
SPDCONF
Speed Configuration for Host
2
2
SPDCONFSelect
NORMAL
Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.
0x0
LS
LS : Low Speed
0x1
HS
HS : High Speed capable
0x2
FS
Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.
0x3
HSTM
HSTM: High Speed Test Mode (force high-speed mode for test mode)
0x3
TSTJ
Test mode J
5
1
TSTK
Test mode K
6
1
TSTPCKT
Test packet mode
7
1
UPRSM
Upstream Resume
1
1
VBUSOK
VBUS is OK
10
1
DADD
DEVICE Device Address
0xA
8
read-write
n
0x0
0x0
ADDEN
Device Address Enable
7
1
DADD
Device Address
0
7
DESCADD
Descriptor Address
0x24
32
read-write
n
0x0
0x0
DESCADD
Descriptor Address Value
0
32
EPCFG
DEVICE_ENDPOINT End Point Configuration
0x0
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG0
DEVICE End Point Configuration
0x100
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG1
DEVICE End Point Configuration
0x120
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG2
DEVICE End Point Configuration
0x140
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG3
DEVICE End Point Configuration
0x160
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG4
DEVICE End Point Configuration
0x180
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG5
DEVICE End Point Configuration
0x1A0
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG6
DEVICE End Point Configuration
0x1C0
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPCFG7
DEVICE End Point Configuration
0x1E0
8
read-write
n
0x0
0x0
EPTYPE0
End Point Type0
0
3
EPTYPE1
End Point Type1
4
3
NYETDIS
NYET Token Disable
7
1
EPINTENCLR
DEVICE_ENDPOINT End Point Interrupt Clear Flag
0x8
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR0
DEVICE End Point Interrupt Clear Flag
0x108
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR1
DEVICE End Point Interrupt Clear Flag
0x128
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR2
DEVICE End Point Interrupt Clear Flag
0x148
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR3
DEVICE End Point Interrupt Clear Flag
0x168
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR4
DEVICE End Point Interrupt Clear Flag
0x188
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR5
DEVICE End Point Interrupt Clear Flag
0x1A8
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR6
DEVICE End Point Interrupt Clear Flag
0x1C8
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENCLR7
DEVICE End Point Interrupt Clear Flag
0x1E8
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Disable
4
1
STALL0
Stall 0 In/Out Interrupt Disable
5
1
STALL1
Stall 1 In/Out Interrupt Disable
6
1
TRCPT0
Transfer Complete 0 Interrupt Disable
0
1
TRCPT1
Transfer Complete 1 Interrupt Disable
1
1
TRFAIL0
Error Flow 0 Interrupt Disable
2
1
TRFAIL1
Error Flow 1 Interrupt Disable
3
1
EPINTENSET
DEVICE_ENDPOINT End Point Interrupt Set Flag
0x9
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET0
DEVICE End Point Interrupt Set Flag
0x109
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET1
DEVICE End Point Interrupt Set Flag
0x129
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET2
DEVICE End Point Interrupt Set Flag
0x149
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET3
DEVICE End Point Interrupt Set Flag
0x169
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET4
DEVICE End Point Interrupt Set Flag
0x189
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET5
DEVICE End Point Interrupt Set Flag
0x1A9
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET6
DEVICE End Point Interrupt Set Flag
0x1C9
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTENSET7
DEVICE End Point Interrupt Set Flag
0x1E9
8
read-write
n
0x0
0x0
RXSTP
Received Setup Interrupt Enable
4
1
STALL0
Stall 0 In/out Interrupt enable
5
1
STALL1
Stall 1 In/out Interrupt enable
6
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL0
Error Flow 0 Interrupt Enable
2
1
TRFAIL1
Error Flow 1 Interrupt Enable
3
1
EPINTFLAG
DEVICE_ENDPOINT End Point Interrupt Flag
0x7
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG0
DEVICE End Point Interrupt Flag
0x107
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG1
DEVICE End Point Interrupt Flag
0x127
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG2
DEVICE End Point Interrupt Flag
0x147
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG3
DEVICE End Point Interrupt Flag
0x167
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG4
DEVICE End Point Interrupt Flag
0x187
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG5
DEVICE End Point Interrupt Flag
0x1A7
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG6
DEVICE End Point Interrupt Flag
0x1C7
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTFLAG7
DEVICE End Point Interrupt Flag
0x1E7
8
read-write
n
0x0
0x0
RXSTP
Received Setup
4
1
STALL0
Stall 0 In/out
5
1
STALL1
Stall 1 In/out
6
1
TRCPT0
Transfer Complete 0
0
1
TRCPT1
Transfer Complete 1
1
1
TRFAIL0
Error Flow 0
2
1
TRFAIL1
Error Flow 1
3
1
EPINTSMRY
DEVICE End Point Interrupt Summary
0x20
16
read-only
n
0x0
0x0
EPINT0
End Point 0 Interrupt
0
1
read-only
EPINT1
End Point 1 Interrupt
1
1
read-only
EPINT2
End Point 2 Interrupt
2
1
read-only
EPINT3
End Point 3 Interrupt
3
1
read-only
EPINT4
End Point 4 Interrupt
4
1
read-only
EPINT5
End Point 5 Interrupt
5
1
read-only
EPINT6
End Point 6 Interrupt
6
1
read-only
EPINT7
End Point 7 Interrupt
7
1
read-only
EPSTATUS
DEVICE_ENDPOINT End Point Pipe Status
0x6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
BK1RDY
Bank 1 ready
7
1
CURBK
Current Bank
2
1
DTGLIN
Data Toggle In
1
1
DTGLOUT
Data Toggle Out
0
1
STALLRQ0
Stall 0 Request
4
1
STALLRQ1
Stall 1 Request
5
1
EPSTATUS0
DEVICE End Point Pipe Status
0x106
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS1
DEVICE End Point Pipe Status
0x126
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS2
DEVICE End Point Pipe Status
0x146
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS3
DEVICE End Point Pipe Status
0x166
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS4
DEVICE End Point Pipe Status
0x186
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS5
DEVICE End Point Pipe Status
0x1A6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS6
DEVICE End Point Pipe Status
0x1C6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUS7
DEVICE End Point Pipe Status
0x1E6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGLIN
Data Toggle In
1
1
read-only
DTGLOUT
Data Toggle Out
0
1
read-only
STALLRQ0
Stall 0 Request
4
1
read-only
STALLRQ1
Stall 1 Request
5
1
read-only
EPSTATUSCLR
DEVICE_ENDPOINT End Point Pipe Status Clear
0x4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
BK1RDY
Bank 1 Ready Clear
7
1
CURBK
Curren Bank Clear
2
1
DTGLIN
Data Toggle IN Clear
1
1
DTGLOUT
Data Toggle OUT Clear
0
1
STALLRQ0
Stall 0 Request Clear
4
1
STALLRQ1
Stall 1 Request Clear
5
1
EPSTATUSCLR0
DEVICE End Point Pipe Status Clear
0x104
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR1
DEVICE End Point Pipe Status Clear
0x124
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR2
DEVICE End Point Pipe Status Clear
0x144
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR3
DEVICE End Point Pipe Status Clear
0x164
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR4
DEVICE End Point Pipe Status Clear
0x184
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR5
DEVICE End Point Pipe Status Clear
0x1A4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR6
DEVICE End Point Pipe Status Clear
0x1C4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSCLR7
DEVICE End Point Pipe Status Clear
0x1E4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank Clear
2
1
write-only
DTGLIN
Data Toggle IN Clear
1
1
write-only
DTGLOUT
Data Toggle OUT Clear
0
1
write-only
STALLRQ0
Stall 0 Request Clear
4
1
write-only
STALLRQ1
Stall 1 Request Clear
5
1
write-only
EPSTATUSSET
DEVICE_ENDPOINT End Point Pipe Status Set
0x5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
BK1RDY
Bank 1 Ready Set
7
1
CURBK
Current Bank Set
2
1
DTGLIN
Data Toggle IN Set
1
1
DTGLOUT
Data Toggle OUT Set
0
1
STALLRQ0
Stall 0 Request Set
4
1
STALLRQ1
Stall 1 Request Set
5
1
EPSTATUSSET0
DEVICE End Point Pipe Status Set
0x105
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET1
DEVICE End Point Pipe Status Set
0x125
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET2
DEVICE End Point Pipe Status Set
0x145
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET3
DEVICE End Point Pipe Status Set
0x165
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET4
DEVICE End Point Pipe Status Set
0x185
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET5
DEVICE End Point Pipe Status Set
0x1A5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET6
DEVICE End Point Pipe Status Set
0x1C5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
EPSTATUSSET7
DEVICE End Point Pipe Status Set
0x1E5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGLIN
Data Toggle IN Set
1
1
write-only
DTGLOUT
Data Toggle OUT Set
0
1
write-only
STALLRQ0
Stall 0 Request Set
4
1
write-only
STALLRQ1
Stall 1 Request Set
5
1
write-only
FLENHIGH
HOST Host Frame Length
0x12
8
read-only
n
0x0
0x0
FLENHIGH
Frame Length
0
8
read-only
FNUM
HOST Host Frame Number
0x10
16
read-write
n
0x0
0x0
FNCERR
Frame Number CRC Error
15
1
read-only
FNUM
Frame Number
3
11
read-only
MFNUM
Micro Frame Number
0
3
read-only
FSMSTATUS
Finite State Machine Status
0xD
8
read-only
n
0x0
0x0
FSMSTATE
Fine State Machine Status
0
7
read-only
FSMSTATESelect
OFF
OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
0x1
DNRESUME
DNRESUME. Down Stream Resume.
0x10
ON
ON (L0). It corresponds to the Idle and Active states
0x2
UPRESUME
UPRESUME. Up Stream Resume.
0x20
SUSPEND
SUSPEND (L2)
0x4
RESET
RESET. USB lines Reset.
0x40
SLEEP
SLEEP (L1)
0x8
HSOFC
HOST Host Start Of Frame Control
0xA
8
read-write
n
0x0
0x0
FLENC
Frame Length Control
0
4
FLENCE
Frame Length Control Enable
7
1
INTENCLR
HOST Host Interrupt Enable Clear
0x14
16
read-write
n
0x0
0x0
DCONN
Device Connection Interrupt Disable
8
1
DDISC
Device Disconnection Interrupt Disable
9
1
DNRSM
DownStream to Device Interrupt Disable
5
1
EORSM
End Of Resume Interrupt Enable
5
1
EORST
End of Reset Interrupt Enable
3
1
HSOF
Host Start Of Frame Interrupt Disable
2
1
LPMNYET
Link Power Management Not Yet Interrupt Enable
8
1
LPMSUSP
Link Power Management Suspend Interrupt Enable
9
1
MSOF
Micro Start of Frame Interrupt Enable in High Speed Mode
1
1
RAMACER
Ram Access Interrupt Disable
7
1
RST
BUS Reset Interrupt Disable
3
1
SOF
Start Of Frame Interrupt Enable
2
1
SUSPEND
Suspend Interrupt Enable
0
1
UPRSM
Upstream Resume from Device Interrupt Disable
6
1
WAKEUP
Wake Up Interrupt Disable
4
1
INTENSET
HOST Host Interrupt Enable Set
0x18
16
read-write
n
0x0
0x0
DCONN
Link Power Management Interrupt Enable
8
1
DDISC
Device Disconnection Interrupt Enable
9
1
DNRSM
DownStream to the Device Interrupt Enable
5
1
EORSM
End Of Resume Interrupt Enable
5
1
EORST
End of Reset Interrupt Enable
3
1
HSOF
Host Start Of Frame Interrupt Enable
2
1
LPMNYET
Link Power Management Not Yet Interrupt Enable
8
1
LPMSUSP
Link Power Management Suspend Interrupt Enable
9
1
MSOF
Micro Start of Frame Interrupt Enable in High Speed Mode
1
1
RAMACER
Ram Access Interrupt Enable
7
1
RST
Bus Reset Interrupt Enable
3
1
SOF
Start Of Frame Interrupt Enable
2
1
SUSPEND
Suspend Interrupt Enable
0
1
UPRSM
Upstream Resume fromthe device Interrupt Enable
6
1
WAKEUP
Wake Up Interrupt Enable
4
1
INTFLAG
HOST Host Interrupt Flag
0x1C
16
read-write
n
0x0
0x0
DCONN
Device Connection
8
1
DDISC
Device Disconnection
9
1
DNRSM
Downstream
5
1
EORSM
End Of Resume
5
1
EORST
End of Reset
3
1
HSOF
Host Start Of Frame
2
1
LPMNYET
Link Power Management Not Yet
8
1
LPMSUSP
Link Power Management Suspend
9
1
MSOF
Micro Start of Frame in High Speed Mode
1
1
RAMACER
Ram Access
7
1
RST
Bus Reset
3
1
SOF
Start Of Frame
2
1
SUSPEND
Suspend
0
1
UPRSM
Upstream Resume from the Device
6
1
WAKEUP
Wake Up
4
1
PADCAL
USB PAD Calibration
0x28
16
read-write
n
0x0
0x0
TRANSN
USB Pad Transn calibration
6
5
TRANSP
USB Pad Transp calibration
0
5
TRIM
USB Pad Trim calibration
12
3
PCFG
HOST_PIPE End Point Configuration
0x0
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG0
HOST End Point Configuration
0x100
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG1
HOST End Point Configuration
0x120
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG2
HOST End Point Configuration
0x140
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG3
HOST End Point Configuration
0x160
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG4
HOST End Point Configuration
0x180
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG5
HOST End Point Configuration
0x1A0
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG6
HOST End Point Configuration
0x1C0
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PCFG7
HOST End Point Configuration
0x1E0
8
read-write
n
0x0
0x0
BK
Pipe Bank
2
1
PTOKEN
Pipe Token
0
2
PTYPE
Pipe Type
3
3
PINTENCLR
HOST_PIPE Pipe Interrupt Flag Clear
0x8
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR0
HOST Pipe Interrupt Flag Clear
0x108
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR1
HOST Pipe Interrupt Flag Clear
0x128
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR2
HOST Pipe Interrupt Flag Clear
0x148
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR3
HOST Pipe Interrupt Flag Clear
0x168
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR4
HOST Pipe Interrupt Flag Clear
0x188
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR5
HOST Pipe Interrupt Flag Clear
0x1A8
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR6
HOST Pipe Interrupt Flag Clear
0x1C8
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENCLR7
HOST Pipe Interrupt Flag Clear
0x1E8
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Disable
3
1
STALL
Stall Interrupt Disable
5
1
TRCPT0
Transfer Complete 0 Disable
0
1
TRCPT1
Transfer Complete 1 Disable
1
1
TRFAIL
Error Flow Interrupt Disable
2
1
TXSTP
Transmit Setup Interrupt Disable
4
1
PINTENSET
HOST_PIPE Pipe Interrupt Flag Set
0x9
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET0
HOST Pipe Interrupt Flag Set
0x109
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET1
HOST Pipe Interrupt Flag Set
0x129
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET2
HOST Pipe Interrupt Flag Set
0x149
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET3
HOST Pipe Interrupt Flag Set
0x169
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET4
HOST Pipe Interrupt Flag Set
0x189
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET5
HOST Pipe Interrupt Flag Set
0x1A9
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET6
HOST Pipe Interrupt Flag Set
0x1C9
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTENSET7
HOST Pipe Interrupt Flag Set
0x1E9
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Enable
3
1
STALL
Stall Interrupt Enable
5
1
TRCPT0
Transfer Complete 0 Interrupt Enable
0
1
TRCPT1
Transfer Complete 1 Interrupt Enable
1
1
TRFAIL
Error Flow Interrupt Enable
2
1
TXSTP
Transmit Setup Interrupt Enable
4
1
PINTFLAG
HOST_PIPE Pipe Interrupt Flag
0x7
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG0
HOST Pipe Interrupt Flag
0x107
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG1
HOST Pipe Interrupt Flag
0x127
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG2
HOST Pipe Interrupt Flag
0x147
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG3
HOST Pipe Interrupt Flag
0x167
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG4
HOST Pipe Interrupt Flag
0x187
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG5
HOST Pipe Interrupt Flag
0x1A7
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG6
HOST Pipe Interrupt Flag
0x1C7
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTFLAG7
HOST Pipe Interrupt Flag
0x1E7
8
read-write
n
0x0
0x0
PERR
Pipe Error Interrupt Flag
3
1
STALL
Stall Interrupt Flag
5
1
TRCPT0
Transfer Complete 0 Interrupt Flag
0
1
TRCPT1
Transfer Complete 1 Interrupt Flag
1
1
TRFAIL
Error Flow Interrupt Flag
2
1
TXSTP
Transmit Setup Interrupt Flag
4
1
PINTSMRY
HOST Pipe Interrupt Summary
0x20
16
read-only
n
0x0
0x0
EPINT0
Pipe 0 Interrupt
0
1
read-only
EPINT1
Pipe 1 Interrupt
1
1
read-only
EPINT2
Pipe 2 Interrupt
2
1
read-only
EPINT3
Pipe 3 Interrupt
3
1
read-only
EPINT4
Pipe 4 Interrupt
4
1
read-only
EPINT5
Pipe 5 Interrupt
5
1
read-only
EPINT6
Pipe 6 Interrupt
6
1
read-only
EPINT7
Pipe 7 Interrupt
7
1
read-only
PSTATUS
HOST_PIPE End Point Pipe Status
0x6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
BK1RDY
Bank 1 ready
7
1
CURBK
Current Bank
2
1
DTGL
Data Toggle
0
1
PFREEZE
Pipe Freeze
4
1
PSTATUS0
HOST End Point Pipe Status
0x106
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS1
HOST End Point Pipe Status
0x126
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS2
HOST End Point Pipe Status
0x146
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS3
HOST End Point Pipe Status
0x166
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS4
HOST End Point Pipe Status
0x186
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS5
HOST End Point Pipe Status
0x1A6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS6
HOST End Point Pipe Status
0x1C6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUS7
HOST End Point Pipe Status
0x1E6
8
read-only
n
0x0
0x0
BK0RDY
Bank 0 ready
6
1
read-only
BK1RDY
Bank 1 ready
7
1
read-only
CURBK
Current Bank
2
1
read-only
DTGL
Data Toggle
0
1
read-only
PFREEZE
Pipe Freeze
4
1
read-only
PSTATUSCLR
HOST_PIPE End Point Pipe Status Clear
0x4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
BK1RDY
Bank 1 Ready Clear
7
1
CURBK
Curren Bank clear
2
1
DTGL
Data Toggle clear
0
1
PFREEZE
Pipe Freeze Clear
4
1
PSTATUSCLR0
HOST End Point Pipe Status Clear
0x104
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR1
HOST End Point Pipe Status Clear
0x124
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR2
HOST End Point Pipe Status Clear
0x144
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR3
HOST End Point Pipe Status Clear
0x164
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR4
HOST End Point Pipe Status Clear
0x184
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR5
HOST End Point Pipe Status Clear
0x1A4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR6
HOST End Point Pipe Status Clear
0x1C4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSCLR7
HOST End Point Pipe Status Clear
0x1E4
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Clear
6
1
write-only
BK1RDY
Bank 1 Ready Clear
7
1
write-only
CURBK
Curren Bank clear
2
1
write-only
DTGL
Data Toggle clear
0
1
read-only
PFREEZE
Pipe Freeze Clear
4
1
write-only
PSTATUSSET
HOST_PIPE End Point Pipe Status Set
0x5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
BK1RDY
Bank 1 Ready Set
7
1
CURBK
Current Bank Set
2
1
DTGL
Data Toggle Set
0
1
PFREEZE
Pipe Freeze Set
4
1
PSTATUSSET0
HOST End Point Pipe Status Set
0x105
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET1
HOST End Point Pipe Status Set
0x125
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET2
HOST End Point Pipe Status Set
0x145
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET3
HOST End Point Pipe Status Set
0x165
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET4
HOST End Point Pipe Status Set
0x185
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET5
HOST End Point Pipe Status Set
0x1A5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET6
HOST End Point Pipe Status Set
0x1C5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
PSTATUSSET7
HOST End Point Pipe Status Set
0x1E5
8
write-only
n
0x0
0x0
BK0RDY
Bank 0 Ready Set
6
1
write-only
BK1RDY
Bank 1 Ready Set
7
1
write-only
CURBK
Current Bank Set
2
1
write-only
DTGL
Data Toggle Set
0
1
write-only
PFREEZE
Pipe Freeze Set
4
1
write-only
QOSCTRL
USB Quality Of Service
0x3
8
read-write
n
0x0
0x0
CQOS
Configuration Quality of Service
0
2
CQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
DQOS
Data Quality of Service
2
2
DQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
STATUS
HOST Status
0xC
8
read-write
n
0x0
0x0
LINESTATE
USB Line State Status
6
2
read-only
LINESTATESelect
0
SE0/RESET
0x0
1
FS-J or LS-K State
0x1
2
FS-K or LS-J State
0x2
SPEED
Speed Status
2
2
read-only
SPEEDSelect
FS
Full-speed mode
0x0
HS
High-speed mode
0x1
LS
Low-speed mode
0x2
SYNCBUSY
Synchronization Busy
0x2
8
read-only
n
0x0
0x0
ENABLE
Enable Synchronization Busy
1
1
read-only
SWRST
Software Reset Synchronization Busy
0
1
read-only
WDT
Watchdog Timer
WDT
0x0
0x0
0x9
registers
n
0x0
0x9
registers
n
0x0
0x9
registers
n
0x0
0x9
registers
n
WDT_INTREQ
2
WDT
2
CLEAR
Clear
0x8
8
write-only
n
0x0
0x0
CLEAR
Watchdog Clear
0
8
write-only
CLEARSelect
KEY
Clear Key
0xA5
CONFIG
Configuration
0x1
8
read-write
n
0x0
0x0
PER
Time-Out Period
0
4
PERSelect
8
8 clock cycles
0x0
16
16 clock cycles
0x1
32
32 clock cycles
0x2
64
64 clock cycles
0x3
128
128 clock cycles
0x4
256
256 clock cycles
0x5
512
512 clock cycles
0x6
1K
1024 clock cycles
0x7
2K
2048 clock cycles
0x8
4K
4096 clock cycles
0x9
8K
8192 clock cycles
0xA
16K
16384 clock cycles
0xB
WINDOW
Window Mode Time-Out Period
4
4
WINDOWSelect
8
8 clock cycles
0x0
16
16 clock cycles
0x1
32
32 clock cycles
0x2
64
64 clock cycles
0x3
128
128 clock cycles
0x4
256
256 clock cycles
0x5
512
512 clock cycles
0x6
1K
1024 clock cycles
0x7
2K
2048 clock cycles
0x8
4K
4096 clock cycles
0x9
8K
8192 clock cycles
0xA
16K
16384 clock cycles
0xB
CTRL
Control
0x0
8
read-write
n
0x0
0x0
ALWAYSON
Always-On
7
1
ENABLE
Enable
1
1
WEN
Watchdog Timer Window Mode Enable
2
1
EWCTRL
Early Warning Interrupt Control
0x2
8
read-write
n
0x0
0x0
EWOFFSET
Early Warning Interrupt Time Offset
0
4
EWOFFSETSelect
8
8 clock cycles
0x0
16
16 clock cycles
0x1
32
32 clock cycles
0x2
64
64 clock cycles
0x3
128
128 clock cycles
0x4
256
256 clock cycles
0x5
512
512 clock cycles
0x6
1K
1024 clock cycles
0x7
2K
2048 clock cycles
0x8
4K
4096 clock cycles
0x9
8K
8192 clock cycles
0xA
16K
16384 clock cycles
0xB
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
EW
Early Warning Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
EW
Early Warning Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
EW
Early Warning
0
1
STATUS
Status
0x7
8
read-only
n
0x0
0x0
SYNCBUSY
Synchronization Busy
7
1
read-only